Any body can explain whats wrong with this simple code ERROR:Xst:827

Discussion in 'VHDL' started by chanson, Oct 7, 2009.

  1. chanson

    chanson

    Joined:
    Oct 30, 2008
    Messages:
    4
    process (clk, rst)
    begin
    if rst'event and rst = '0' then
    Q <='0';
    elsif clk = '1' then
    Q<=D
    end process.


    it doesnt seem voilate the rules:

    The synchronous element description is based on the 'event VHDL attribute. In order for XST to infer a synchronous element, the 'event VHDL attribute must be present in the topmost "IF" statement of your process. Furthermore, there should be no embedded 'event statements within a process.

    but how come XST doesnt allow to monitor the rst falling edge triger. it gave me error : ERROR:Xst:827

    I modify the code like the following and it works. anybody can explain?

    process (clk, rst)
    begin
    if rst = '0' then
    Q <='0';
    elsif clk'event and clk = '1' then
    Q<=D
    end process.
     
    chanson, Oct 7, 2009
    #1
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  2. chanson

    chanson

    Joined:
    Oct 30, 2008
    Messages:
    4
    anybody help pls?
     
    chanson, Oct 9, 2009
    #2
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  3. chanson

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
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    Denmark
    If your expect a VHDL code to be executed as a "normal" software program would both "programs" be ok.

    However will your VHDL be synthesized into hardware - and you can't have a F/F which react at a rising_edge and does some ELSE when no rising_edge.

    Jeppe
     
    jeppe, Oct 9, 2009
    #3
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