Any idea on VHDL and C cosimulation?Thanks

[Lee]

How to do cosimulation for VHDL/Verilog and C?Thanks,

 

[Uncle Noah]

How to do cosimulation for VHDL/Verilog and C?Thanks,

FLI (Foreign Language Interface) in Modelsim.

Nikos Kavvadias

 

[Maarten Verhage]

You'll need the SE version of ModelSim and Visual C++ for a Windows
platform. For Linux it's different.

 

[Guenter Dannoritzer]

Hello,

FLI (Foreign Language Interface) in Modelsim.

Nikos Kavvadias

After becoming aware of the PLI functionality in Verilog I started
looking for something similar in VHDL. I found that there is a PLI
specification as well, but after searching for simulators that support
it I only found that a few commercial simulators like ModelSim or Rivera
have it. And there, only the high end version of the simulator has it
implemented. Also it seems like to run under a different name. Like in
ModelSim it is called Foreign Language Interface.

On the other side in Verilog it seems to be pretty common, every
simulator you can find seems to have a PLI and there are tons of books
available.

Do the VHDL developer not use or like to use the PLI?

If so many Verilog developer like to use it, how come it is not so
widely used in VHDL?

How else is coverification done in VHDL?

Thanks for the thoughts.

Guenter

 

[Mike Treseler]

Do the VHDL developer not use or like to use the PLI?

I have found no need for it.

If so many Verilog developer like to use it, how come it is not so
widely used in VHDL?

Some developers choose Verilog based on C language expertise.

How else is coverification done in VHDL?

Code coverage is built-in to modelsim.

-- Mike Treseler

 

[DoesntMatter]

Hello,





After becoming aware of the PLI functionality in Verilog I started
looking for something similar in VHDL. I found that there is a PLI
specification as well, but after searching for simulators that support
it I only found that a few commercial simulators like ModelSim or Rivera
have it. And there, only the high end version of the simulator has it
implemented. Also it seems like to run under a different name. Like in
ModelSim it is called Foreign Language Interface.

On the other side in Verilog it seems to be pretty common, every
simulator you can find seems to have a PLI and there are tons of books
available.

Do the VHDL developer not use or like to use the PLI?

If so many Verilog developer like to use it, how come it is not so
widely used in VHDL?

How else is coverification done in VHDL?

Thanks for the thoughts.

Guenter

The same way : via C-interface.

In practice the VHDL C-interface is much less standardized then the
Verilog PLI. But as the basic functionality of all those C-interfaces is
not that different (read/write variables , update/read signals ,
implementing foreign procedures , implementing foreign architectures
....) , making an abstraction layer over some simulators is not
impossible. Been there.

Jos De Laender

 

[Uncle Noah]

In practice the VHDL C-interface is much less standardized then the
Verilog PLI... Been there.

Jos De Laender

True. For VHDL this interface to C functions in called VHPI. To my knowledge
it has not been standardized yet. Draft of the standard exists.

A few simulators like Active-HDL of Aldec Inc. reportedly support VHPI.

Uncle "The G.B. Man" Noah

 

[Peter Sommerfeld]

Aldec Active-HDL supports VHPI, which seems very similar to PLI.

I hope to use it to retarget the host API to talk to my testbench
instead of real hardware which would be really useful for me. I don't
know if that is possible yet.

-- Pete

 

[Thomas Stanka]

On the other side in Verilog it seems to be pretty common, every
simulator you can find seems to have a PLI and there are tons of books
available.

Do the VHDL developer not use or like to use the PLI?

If so many Verilog developer like to use it, how come it is not so
widely used in VHDL?

Maybe thats a question of needs?
You don't need to use C to program a testbench in VHDL. It may be
comfortable to use existing C code, but you could program any
functionality in VHDL.
I think it's a bit harder to do complex testbenches in Verilog [1], so
it maybe useful for Verilog user to build testbenches in C. Another
point may be that Verilog has many in common with C, where VHLD is
derived form ADA and has a lot of incompatibilities to C.

How else is coverification done in VHDL?

If you don't like to use a simulator with an interface to C (like
modelsim), you could interchange via textfiles. I don't know if it is
possible to change the content of stimuli files for simulators during
runtime, but it is common to generate stimuli with C (or any other
language), simulate with this files and use some other programs to
evaluate the simulation output.

bye Thomas

 

[Wendell Petersen]

I do not know much about it, but you might look into ghdl.