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How to do cosimulation for VHDL/Verilog and C?Thanks,
How to do cosimulation for VHDL/Verilog and C?Thanks,
Uncle said:FLI (Foreign Language Interface) in Modelsim.
Nikos Kavvadias
Guenter said:Do the VHDL developer not use or like to use the PLI?
If so many Verilog developer like to use it, how come it is not so
widely used in VHDL?
How else is coverification done in VHDL?
Guenter said:Hello,
After becoming aware of the PLI functionality in Verilog I started
looking for something similar in VHDL. I found that there is a PLI
specification as well, but after searching for simulators that support
it I only found that a few commercial simulators like ModelSim or Rivera
have it. And there, only the high end version of the simulator has it
implemented. Also it seems like to run under a different name. Like in
ModelSim it is called Foreign Language Interface.
On the other side in Verilog it seems to be pretty common, every
simulator you can find seems to have a PLI and there are tons of books
available.
Do the VHDL developer not use or like to use the PLI?
If so many Verilog developer like to use it, how come it is not so
widely used in VHDL?
How else is coverification done in VHDL?
Thanks for the thoughts.
Guenter
In practice the VHDL C-interface is much less standardized then the
Verilog PLI... Been there.
Jos De Laender
Guenter Dannoritzer said:On the other side in Verilog it seems to be pretty common, every
simulator you can find seems to have a PLI and there are tons of books
available.
Do the VHDL developer not use or like to use the PLI?
If so many Verilog developer like to use it, how come it is not so
widely used in VHDL?
How else is coverification done in VHDL?
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