any simple way to load test vector in testbench that contains decimal format?

[py]

Let say I have a vector file in the following format

#input1 input2 input3
123 456 7
111 0 111
#end

Is there any method or package that would convert the decimal number into std_logic_vector? Or would it be too much effort and we should just stick with binary/hex?


Thanks,

 

[Tricky]

Let say I have a vector file in the following format



#input1 input2 input3

123 456 7

111 0 111

#end



Is there any method or package that would convert the decimal number into std_logic_vector? Or would it be too much effort and we should just stick with binary/hex?





Thanks,

read them in as an integer using std.textio, and then use numeric_std to convert to std_logic_vector

slv <= std_logic_vector( to_unsigned( input, slv'length) ) ;

BUT

if they are numbers in the test vector file, why are you using std_logic_vectors in your VHDL? why not integers or unsigned?

 

[Nicolas Matringe]

Le 24/10/2012 11:16, Tricky a écrit :

if they are numbers in the test vector file, why are you using std_logic_vectors in your VHDL? why not integers or unsigned?

On a top-level entity it is better practice to use sl/slv ports only
because post-p&r models won't use anything else.
In case you want to simulate your p&r result you will then be able to
replace the source entity with the model without any change to the
testbench.

Nicolas

 

[Pontus]

Let say I have a vector file in the following format

#input1 input2 input3
123     456      7
111       0    111
#end

Is there any method or package that would convert the decimal number intostd_logic_vector? Or would it be too much effort and we should just stick with binary/hex?

Thanks,

If you attempt to parse the test vector file (TVF) with a VHDL
code written by you you will need to handle all the possible
irregularities of the test vector file (TVF) yourself.
What I mean is that your TVF *has* syntax, and so you can have
syntax errors...
Discovering those after a long simulation run may hurt.

Instead, try to embed your test vectors into a valid VHDL package
You will need a header part (package xyz is ...) declaring
types (arrays of integers) and then your TVF with correct
syntax, i.e. commas between values etc. Finnaly an tail part
(end package xyz.

The big pro is that you will catch those syntax errors at compile
time.

Converting the integers to slv's is best done using numeric_std
package (e.g. std_logic_vector(to_unsigned(int,16)) )

-- HTH Pontus

 

[rickman]

Hi py!

into std_logic_vector? Or would it be too much effort and we should just
stick with binary/hex?

Maybe have a look at <http://bear.ces.case.edu/VHDL/index.html>. This is
a package to have ANSI C - like file I/O in VHDL. It is often more
easier to read than the standard VHDL methods.

Ralf

Great! Thanks

Rick