any sites in which asynchronous VHDL examples are given

Discussion in 'VHDL' started by chaitanyakurmala@gmail.com, Jul 5, 2006.

  1. Guest

    i want to design an asynchronous multiplier by using modified booths
    algorithm.so initially i want to design an normal adder and a carry
    look ahead adder in asynchronous style in VHDL.any help is appreciates
     
    , Jul 5, 2006
    #1
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  2. KJ Guest

    <> wrote in message
    news:...
    >i want to design an asynchronous multiplier by using modified booths
    > algorithm.


    Maybe you have your reasons for wanting to design the multiplier yourself
    but if not then, assuming that 'a', 'b' and 'product' are unsigned types of
    the appropriate widths and that you include the ieee.numeric_std library,
    then combinatorial multiplication in VHDL is simply...

    product <= a * b;

    > so initially i want to design an normal adder and a carry
    > look ahead adder in asynchronous style in VHDL.any help is appreciates
    >


    Again, maybe you have your reasons for wanting to design the adder yourself
    but if not then, assuming that 'a', 'b' and 'sum' are unsigned types of the
    appropriate widths and that you include the ieee.numeric_std library, then
    combinatorial addition in VHDL is simply...

    sum <= a + b;

    If you do have your reasons for wanting to design the individual parts
    yourself, then I would suggest googling until you find the algorithm
    definitions that you are looking for.

    KJ
     
    KJ, Jul 5, 2006
    #2
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  3. Frank Buss Guest

    wrote:

    > i want to design an asynchronous multiplier by using modified booths
    > algorithm.so initially i want to design an normal adder and a carry
    > look ahead adder in asynchronous style in VHDL.any help is appreciates


    This sounds like a homework, so if you want to learn something, don't read
    this text :)

    This is my 2nd VHDL program, so the code might not look like other VHDL
    programs and there are faster algorithms. Of course, the best would be to
    use simply "*" and let the synthesizer decide how to implement it, e.g.
    using integrated multiplier modules of some FPGAs.

    One thing which I don't understand is that Xilinx ISE says "unexpected if",
    if I try to inline the function shift_add. Looks like it says this for even
    the simplest "if" command inside a "for ... generate" block.

    -- halfadder
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity halfadder is
    port(
    a, b : in std_logic;
    sum, carry : out std_logic);
    end entity halfadder;

    architecture rtl of halfadder is
    begin
    sum <= a xor b;
    carry <= a and b;
    end architecture rtl;


    -- fulladder
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity fulladder is
    port(
    a, b, carry_in: in std_logic;
    sum, carry_out: out std_logic);
    end entity fulladder;

    architecture rtl of fulladder is
    signal sum1, carry1, carry2: std_logic;

    begin
    halfadder1: entity halfadder
    port map(
    a => a,
    b => b,
    sum => sum1,
    carry => carry1);

    halfadder2: entity halfadder
    port map(
    a => sum1,
    b => carry_in,
    sum => sum,
    carry => carry2);

    carry_out <= carry1 or carry2;
    end architecture rtl;


    -- adder
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity adder is
    generic (bits: integer);
    port(
    a, b: in unsigned((bits - 1) downto 0);
    sum: out unsigned((bits - 1) downto 0));
    end entity adder;

    architecture rtl of adder is
    signal carries: unsigned((bits - 2) downto 0);

    begin
    first_fulladder: entity fulladder
    port map(
    a => a(0),
    b => b(0),
    sum => sum(0),
    carry_in => '0',
    carry_out => carries(0));

    adders: for i in 1 to bits - 2 generate
    fulladder_n: entity fulladder
    port map(
    a => a(i),
    b => b(i),
    sum => sum(i),
    carry_in => carries(i - 1),
    carry_out => carries(i));
    end generate;

    last_fulladder: entity fulladder
    port map(
    a => a(bits - 1),
    b => b(bits - 1),
    sum => sum(bits - 1),
    carry_in => carries(bits - 2),
    carry_out => open);
    end architecture rtl;


    -- multiplier
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity multiplier is
    generic (bits: integer);
    port(
    a, b: in unsigned((bits - 1) downto 0);
    product: out unsigned((2 * bits - 1) downto 0));
    end entity multiplier;

    architecture rtl of multiplier is
    subtype result_type is unsigned((2 * bits - 1) downto 0);
    type add_signals is array(0 to (bits - 1)) of result_type;
    type sum_signals is array(0 to (bits - 3)) of result_type;
    signal add: add_signals;
    signal sum: sum_signals;

    function shift_add(shift: integer; bits: integer; b: unsigned)
    return unsigned is
    variable result: unsigned(2 * bits - 1 downto 0);
    begin
    if shift < bits then
    for i in 0 to bits - shift - 1 loop
    result(2 * bits - 1 - i) := '0';
    end loop;
    end if;
    for i in 0 to bits - 1 loop
    result(i + shift) := b(i);
    end loop;
    if shift > 0 then
    for i in 0 to shift - 1 loop
    result(i) := '0';
    end loop;
    end if;
    return result;
    end shift_add;

    begin
    first_adder: entity adder
    generic map(bits => 2 * bits)
    port map(
    a => add(0),
    b => add(1),
    sum => sum(0));
    adders: for i in 1 to bits - 3 generate
    adder_n: entity adder
    generic map(bits => 2 * bits)
    port map(
    a => sum(i - 1),
    b => add(i + 1),
    sum => sum(i));
    end generate;
    last_adder: entity adder
    generic map(bits => 2 * bits)
    port map(
    a => sum(bits - 3),
    b => add(bits - 1),
    sum => product);
    adds: for i in 0 to bits - 1 generate
    add(i) <= shift_add(i, bits, a) when b(i) = '1'
    else to_unsigned(0, 2 * bits - 1);
    end generate;
    end architecture rtl;


    -- test
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity test is
    port(
    led : out unsigned(7 downto 0);
    switch : in unsigned(7 downto 0));
    end entity test;

    architecture rtl of test is
    begin
    my_multiplier: entity multiplier
    generic map(bits => 4)
    port map(
    a => switch(3 downto 0),
    b => switch(7 downto 4),
    product => led(7 downto 0));
    end architecture rtl;

    --
    Frank Buss,
    http://www.frank-buss.de, http://www.it4-systems.de
     
    Frank Buss, Jul 5, 2006
    #3
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