Arbiter for the wishbone bus

Discussion in 'VHDL' started by Pooja, May 11, 2006.

  1. Pooja

    Pooja Guest

    Hi everyone,

    I have two "blocks" accessing the same wishbone bus, and hence I am
    writing an arbiter which would allow access to only one of the masters
    at a time. I do have a simple implementation of an arbiter, but what I
    don't get is: which signals do I need in order to "enable" one of the
    two masters on the wishbone bus.

    Thanks in advance for any help.
     
    Pooja, May 11, 2006
    #1
    1. Advertising

  2. Pooja wrote:

    > I have two "blocks" accessing the same wishbone bus, and hence I am
    > writing an arbiter which would allow access to only one of the masters
    > at a time. I do have a simple implementation of an arbiter, but what I
    > don't get is: which signals do I need in order to "enable" one of the
    > two masters on the wishbone bus.


    There's an example of an arbiter in the rev B.1 wishbone specification
    itself. Rev B.3 has a different treatment.

    In a nutshell, you just need a mux for the master outputs (CYC_O, STB_O,
    ADR_O, DAT_O, WE_O) whose selector is the output of your arbitrator
    algorithm. Similarly, your selector also determines which master
    receives the ACK_O/ERR_O/RTY_O from the slave. So you're not 'enabling'
    one master as such, simply gating the slave response so that only the
    master which has been granted the bus sees the end of the cycle.

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, May 12, 2006
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Rusty

    Arbiter algorithm

    Rusty, Apr 6, 2005, in forum: VHDL
    Replies:
    5
    Views:
    1,124
    Mike Treseler
    Apr 6, 2005
  2. mungam

    PCI wishbone can bus

    mungam, Mar 10, 2006, in forum: VHDL
    Replies:
    1
    Views:
    604
    Mark McDougall
    Mar 12, 2006
  3. Replies:
    2
    Views:
    3,459
    Pooja
    May 9, 2006
  4. Davy

    Arbiter schemes?

    Davy, Aug 13, 2006, in forum: VHDL
    Replies:
    3
    Views:
    2,409
    Mike Treseler
    Aug 15, 2006
  5. Replies:
    0
    Views:
    734
Loading...

Share This Page