P
parag_paul
hi All,
IN Verilog we can have something like
module a ( a, .b(v1,v2,v3), c);
in v1,v2,v3;
thus b1 becomes a 3 bit vector. Is that possible in VHDL
If yes can you show me the method. 1076-2000 VHDL standard does not
say anything about it though.
-Parag
IN Verilog we can have something like
module a ( a, .b(v1,v2,v3), c);
in v1,v2,v3;
thus b1 becomes a 3 bit vector. Is that possible in VHDL
If yes can you show me the method. 1076-2000 VHDL standard does not
say anything about it though.
-Parag