Are concat ports supported in VHDL

Discussion in 'VHDL' started by parag_paul@hotmail.com, Nov 8, 2007.

  1. Guest

    hi All,
    IN Verilog we can have something like

    module a ( a, .b(v1,v2,v3), c);

    in v1,v2,v3;

    thus b1 becomes a 3 bit vector. Is that possible in VHDL
    If yes can you show me the method. 1076-2000 VHDL standard does not
    say anything about it though.
    -Parag
     
    , Nov 8, 2007
    #1
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  2. Andy Guest

    On Nov 8, 1:25 pm, "" <>
    wrote:
    > hi All,
    > IN Verilog we can have something like
    >
    > module a ( a, .b(v1,v2,v3), c);
    >
    > in v1,v2,v3;
    >
    > thus b1 becomes a 3 bit vector. Is that possible in VHDL
    > If yes can you show me the method. 1076-2000 VHDL standard does not
    > say anything about it though.
    > -Parag


    You can alias bits of a vector port, but you cannot alias a vector of
    single-bit ports.

    Andy
     
    Andy, Nov 8, 2007
    #2
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  3. Guest

    On Nov 8, 1:07 pm, Andy <> wrote:
    > On Nov 8, 1:25 pm, "" <>
    > wrote:
    >
    > > hi All,
    > > IN Verilog we can have something like

    >
    > > module a ( a, .b(v1,v2,v3), c);

    >
    > > in v1,v2,v3;

    >
    > > thus b1 becomes a 3 bit vector. Is that possible in VHDL
    > > If yes can you show me the method. 1076-2000 VHDL standard does not
    > > say anything about it though.
    > > -Parag

    >
    > You can alias bits of a vector port, but you cannot alias a vector of
    > single-bit ports.
    >
    > Andy


    I am bit unfamiliar with, the terms, aliasing bits of vector port, Do
    you mean blasting the vector bits to different ports
     
    , Nov 8, 2007
    #3
  4. Tricky Guest

    On 8 Nov, 19:25, "" <>
    wrote:
    > hi All,
    > IN Verilog we can have something like
    >
    > module a ( a, .b(v1,v2,v3), c);
    >
    > in v1,v2,v3;
    >
    > thus b1 becomes a 3 bit vector. Is that possible in VHDL
    > If yes can you show me the method. 1076-2000 VHDL standard does not
    > say anything about it though.
    > -Parag


    I think the easiest way in VHDL is to have an intermediate signal
    thats a concatenation of the 3 signal bits.

    signal concat : std_logic_vector(2 downto 0);
    ...
    concat <= v2 & v1 & v0;

    inst : a
    port map (
    a => a,
    b => concat,
    c => c
    );
     
    Tricky, Nov 9, 2007
    #4
  5. On Thu, 08 Nov 2007 19:25:30 -0000, ""
    <> wrote:

    >hi All,
    >IN Verilog we can have something like
    >
    >module a ( a, .b(v1,v2,v3), c);
    >
    >in v1,v2,v3;
    >
    >thus b1 becomes a 3 bit vector. Is that possible in VHDL


    Yes, but not like that. Given a vector port, you can
    associate individual bits or slices:

    entity submodule is
    port (A: in std_logic_vector(7 downto 0); ...);
    end;

    ....
    instance_of_submodule:
    entity work.submodule
    port map (
    A(7) => top_bit,
    A(6 downto 1) => middle_6,
    A(0) => LSB,
    ...

    > 1076-2000 VHDL standard does not
    > say anything about it though.


    It doesn't need to; the rules about port association
    make it clear that the above form is OK.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Nov 9, 2007
    #5
  6. Tricky Guest

    On 9 Nov, 10:20, Tricky <> wrote:
    > On 8 Nov, 19:25, "" <>
    > wrote:
    >
    > > hi All,
    > > IN Verilog we can have something like

    >
    > > module a ( a, .b(v1,v2,v3), c);

    >
    > > in v1,v2,v3;

    >
    > > thus b1 becomes a 3 bit vector. Is that possible in VHDL
    > > If yes can you show me the method. 1076-2000 VHDL standard does not
    > > say anything about it though.
    > > -Parag

    >
    > I think the easiest way in VHDL is to have an intermediate signal
    > thats a concatenation of the 3 signal bits.
    >
    > signal concat : std_logic_vector(2 downto 0);
    > ..
    > concat <= v2 & v1 & v0;
    >
    > inst : a
    > port map (
    > a => a,
    > b => concat,
    > c => c
    > );


    Or what Jonathan Said :)
     
    Tricky, Nov 9, 2007
    #6
  7. Andy Guest

    On Nov 8, 5:01 pm, "" <>
    wrote:
    > On Nov 8, 1:07 pm, Andy <> wrote:
    >
    >
    >
    > > On Nov 8, 1:25 pm, "" <>
    > > wrote:

    >
    > > > hi All,
    > > > IN Verilog we can have something like

    >
    > > > module a ( a, .b(v1,v2,v3), c);

    >
    > > > in v1,v2,v3;

    >
    > > > thus b1 becomes a 3 bit vector. Is that possible in VHDL
    > > > If yes can you show me the method. 1076-2000 VHDL standard does not
    > > > say anything about it though.
    > > > -Parag

    >
    > > You can alias bits of a vector port, but you cannot alias a vector of
    > > single-bit ports.

    >
    > > Andy

    >
    > I am bit unfamiliar with, the terms, aliasing bits of vector port, Do
    > you mean blasting the vector bits to different ports


    No, I mean declaring an alias of a single bit of a vector port. You
    can do that, and you can declare other aliases of the other bits.

    What you can't do is declare an alias (of type vector) that is a
    collection of single bit ports.

    To declare an alias is to declare "another name for" some other
    object. You can use the alias wherever and however you could use the
    object it is renaming.

    Andy
     
    Andy, Nov 9, 2007
    #7
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