are the next things are synthesizable?

Discussion in 'VHDL' started by Kapish, Apr 23, 2011.

  1. Kapish

    Kapish

    Joined:
    Apr 23, 2011
    Messages:
    1
    Hi people !!

    I need you help,
    are the next things are synthesizable?
    1. variable
    2. for loop
    3. 2D arrays

    if you know how to replace this things in synthesizable implementations,
    I will be glad if you can write it.

    Thank you all.

    Sorry for mistakes in writing if I had English is not my native language.
    Kapish, Apr 23, 2011
    #1
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  2. Kapish

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Synthesizable

    In general, they are synthesizable if used properly.
    eliascm, Apr 27, 2011
    #2
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