ARM AMBA Designer licensing cost

Discussion in 'VHDL' started by guestuser1, Nov 2, 2008.

  1. guestuser1

    guestuser1 Guest

    A different department at my company handles the ARM licensing.
    I think we need to generate some AHB/AXI interconnect blocks,
    but in order to produce the synthesizeable RTL, we need an
    AMBA_Designer license. (We already have an SOC designer,
    ARM compiler/assembler environment.)

    Due to some stupid politics, I'm trying to find out what it'd cost
    the company to acquire the necessary license to run
    AMBA_Designer, yearly maintenance. Then I can go to the project
    lead and beg, beg, beg. Is this a fixed price, or based on other
    ARM-IP we've already licensed (Cortex R4)?
     
    guestuser1, Nov 2, 2008
    #1
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  2. "guestuser1" <> writes:

    > A different department at my company handles the ARM licensing.
    > I think we need to generate some AHB/AXI interconnect blocks,
    > but in order to produce the synthesizeable RTL, we need an
    > AMBA_Designer license. (We already have an SOC designer,
    > ARM compiler/assembler environment.)


    You don't strictly need AMBA Designer to do that. The bus
    interconnects (PL300 or PL301 or whatever they have now) come with
    scripts to configure address ranges, etc. Writing the configuration
    file and the top-level signal plumbing is of course still a manual
    process.

    Note that SoC Designer and I believe AMBA Designer, too, have been
    sold to Carbon Design. ARM has no business in these tools any more. At
    least not officially. Existing licensees might still be supplied with
    new licenses, though.

    > Due to some stupid politics, I'm trying to find out what it'd cost
    > the company to acquire the necessary license to run
    > AMBA_Designer, yearly maintenance. Then I can go to the project
    > lead and beg, beg, beg. Is this a fixed price, or based on other
    > ARM-IP we've already licensed (Cortex R4)?


    Like with every other EDA tool, everything is negotiable. I'd ask. End
    of quarter coming closer... Doesn't make any sense to quote list
    prices here.

    Regards
    Marcus

    --
    note that "property" can also be used as syntaxtic sugar to reference
    a property, breaking the clean design of verilog; [...]

    (seen on http://www.veripool.com/verilog-mode_news.html)
     
    Marcus Harnisch, Nov 2, 2008
    #2
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  3. guestuser1

    guestuser1 Guest

    "Marcus Harnisch" <> wrote in message
    news:...
    > "guestuser1" <> writes:
    >
    >> A different department at my company handles the ARM licensing.
    >> I think we need to generate some AHB/AXI interconnect blocks,
    >> but in order to produce the synthesizeable RTL, we need an
    >> AMBA_Designer license. (We already have an SOC designer,
    >> ARM compiler/assembler environment.)

    >
    > You don't strictly need AMBA Designer to do that. The bus
    > interconnects (PL300 or PL301 or whatever they have now) come with
    > scripts to configure address ranges, etc. Writing the configuration
    > file and the top-level signal plumbing is of course still a manual
    > process.


    Unfortunately, I need to generate a different interconnect (different #
    ports, AXI-to-AHB on one of them)

    > Note that SoC Designer and I believe AMBA Designer, too, have been
    > sold to Carbon Design. ARM has no business in these tools any more. At
    > least not officially. Existing licensees might still be supplied with
    > new licenses, though.


    Really?!? Doesn't ARM Ltd still handle the RVDS package?

    > Like with every other EDA tool, everything is negotiable. I'd ask. End
    > of quarter coming closer... Doesn't make any sense to quote list
    > prices here.


    Ugh...if only my workplace didn't already hava a sales account.
    There's no way I could just call them up (using my company's name),
    without ARM asking me why I'm not the same contact who usually
    handles licensing...
     
    guestuser1, Nov 8, 2008
    #3
  4. guestuser1

    Chris H Guest

    In message <_%9Rk.4402$>, guestuser1
    <> writes
    >
    >"Marcus Harnisch" <> wrote in message
    >news:...
    >> "guestuser1" <> writes:
    >>
    >>> A different department at my company handles the ARM licensing.
    >>> I think we need to generate some AHB/AXI interconnect blocks,
    >>> but in order to produce the synthesizeable RTL, we need an
    >>> AMBA_Designer license. (We already have an SOC designer,
    >>> ARM compiler/assembler environment.)

    >>
    >> You don't strictly need AMBA Designer to do that. The bus
    >> interconnects (PL300 or PL301 or whatever they have now) come with
    >> scripts to configure address ranges, etc. Writing the configuration
    >> file and the top-level signal plumbing is of course still a manual
    >> process.

    >
    >Unfortunately, I need to generate a different interconnect (different #
    >ports, AXI-to-AHB on one of them)
    >
    >> Note that SoC Designer and I believe AMBA Designer, too, have been
    >> sold to Carbon Design. ARM has no business in these tools any more. At
    >> least not officially. Existing licensees might still be supplied with
    >> new licenses, though.

    >
    >Really?!? Doesn't ARM Ltd still handle the RVDS package?


    Yes they still have the ARM RVDS and the Keil-ARM compiler (almost the
    same beast) but they seem to have sold off all their other tools.


    --
    \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
    \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/
    \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
     
    Chris H, Nov 9, 2008
    #4
  5. Chris H <> writes:

    > Yes they still have the ARM RVDS and the Keil-ARM compiler (almost the
    > same beast) but they seem to have sold off all their other tools.


    Not quite. They still have the System Generator, which works similar
    to SoC Designer but operates at an even higher level. Code executes as
    JIT compiled native machine code and runs extremely fast. It is more a
    SW development than ESL tool.

    Regards
    Marcus

    --
    note that "property" can also be used as syntaxtic sugar to reference
    a property, breaking the clean design of verilog; [...]

    (seen on http://www.veripool.com/verilog-mode_news.html)
     
    Marcus Harnisch, Nov 10, 2008
    #5
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