Array in an entity declaration ?

Discussion in 'VHDL' started by Chabrie, May 9, 2008.

  1. Chabrie

    Chabrie Guest

    Hello togehter,

    in the toplevel design, there is an signal "type array of bytes". The
    Signal Declarations is described below:

    Type ArrayOfBytes is Array (31 downto 0) of std_logic_vector(7 downto 0);
    signal test : ArrayOfBytes ;

    Now I want to use the signal "test" in a subprogram.

    Is there a possibility to add the array of the the toplevel to the port
    describtion of the entity declaration of the subprogram?

    Something like that:

    entity subrogram is

    port ( test: in Array (31 downto 0) of std_logic_vectro (7
    downto 0);

    end entity subprogram;



    Best regards
    Carsten
     
    Chabrie, May 9, 2008
    #1
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  2. Chabrie

    KJ Guest

    On May 9, 4:41 am, Chabrie <>
    wrote:
    > Hello togehter,
    >
    > in the toplevel design, there is an signal "type array of bytes". The
    > Signal Declarations is described below:
    >
    > Type ArrayOfBytes is Array (31 downto 0) of std_logic_vector(7 downto 0);      
    > signal  test    : ArrayOfBytes ;
    >
    > Is there a possibility to add the array of the the toplevel to the port
    > describtion of the entity declaration of the  subprogram?
    >
    > Something like that:
    >
    > entity subrogram is
    >
    >         port ( test: in Array (31 downto 0) of std_logic_vectro (7
    > downto 0);
    >
    > end entity subprogram;
    >


    No, it would be of the form
    entity subrogram is
    port ( test: in ArrayOfBytes);
    end entity subprogram;

    This would imply then that the definition of 'ArrayOfBytes' would have
    to be visible in the entity as well, which means you should move the
    definition out of the architecture where you have it now and put it
    into a package and add a 'use
    work.my_package_that_contains_ArrayOfBytes_definition;' statement.

    KJ
     
    KJ, May 9, 2008
    #2
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  3. Chabrie <> posted
    on Fri, 09 May 2008 10:41:33 +0200:
    |--------------------------------------------------------------------------|
    |"[..] |
    | |
    |Type ArrayOfBytes is Array (31 downto 0) of std_logic_vector(7 downto 0); |
    |signal test : ArrayOfBytes ; |
    | |
    |Now I want to use the signal "test" in a subprogram. |
    | |
    |Is there a possibility to add the array of the the toplevel to the port |
    |describtion of the entity declaration of the subprogram? |
    | |
    |Something like that: |
    | |
    |entity subrogram is |
    | |
    | port ( test: in Array (31 downto 0) of std_logic_vectro (7 |
    |downto 0); |
    | |
    |end entity subprogram;" |
    |--------------------------------------------------------------------------|

    Your toplevel test and your port test should not have incompatible
    types, but you have incorrectly declared the port test to be of
    an anonymous type instead of ArrayOfBytes.

    Regards,
    Colin Paul Gloster
     
    Colin Paul Gloster, May 23, 2008
    #3
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