Array initialisation in vhdl

Discussion in 'VHDL' started by san3885, Apr 27, 2008.

  1. san3885

    san3885

    Joined:
    Apr 27, 2008
    Messages:
    1
    Hi friends....

    i wanted to know whether we can initialise a vhdl array type variable or signal as shown below...
    ===================================
    .....
    type example is array ( 1 to 10, 1 to 10 ) of any type
    signal test: example;
    ....
    ....
    for i is 1 to 10 loop
    for j is 1 to 10 loop
    test(i,j) <= "same 'array type' element"
    end loop
    end loop

    ====================================

    when i tried in ISE 8.2i i got an error as test(i) is invalid array index

    since im a beginner in VHDL ...u guys plz throw some light on this concept :veryprou:
     
    Last edited: Apr 27, 2008
    san3885, Apr 27, 2008
    #1
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  2. san3885

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    would i and j be variables of the type integer?
     
    jeppe, Apr 27, 2008
    #2
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