Array issues

[bryfu]

Hi all,

I have some issues when i do my coding in VHDL.

1st: i instantiate array as follows:

"type data_array is array (1 to 1) of STD_LOGIC_VECTOR (64 DOWNTO 0);
signal data: data_array;"
............
............
after which i use the array as :

"data <= PR_dout;"

where PR_dout is an input of 65 bits long. But i get error that goes :

"Type of data is incompatible with type of PR_dout"

I would appreciate very much if some one can help me in this .

Thank u.

 

[joris]

Maybe you meant,

data(1) <= PR_dout;