Array of bits on to a signal in VHDL

[JSreeniv]

Hi all,
I need some suggestion on writing testbench of non-systhesizable code
I have 32-bit hex word; for example: 0x1000 1000 and this should be
transmitted on rcom_tx output signal using Manchester encoding(for 1--

10, 0-->01). 32-bit hex word in Binary forma is

b^0001_0000_0000_0000_0001_0000_0000_0000
Now the manchester form is(MSB-->LSB):
01010110_01010101_01010101_01010101_10010101_01010101_01010101_01010101
for every bit of manchester there is 50 ns +/- 15 ns delay
so what i am writing as my concepts of VHDL: For MSB(01010110)
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
----------------------------------------------
Here i need confirmation that: Is there any other easy way of writing
this data on rcom_tx with delay. And also suggest how to represent the
tolerance value with this.

Please give me suggestions
Sreeniv

 

[Shanmugavel D]

Hi all,
I need some suggestion on writing testbench of non-systhesizable code
I have 32-bit hex word; for example: 0x1000 1000 and this should be
transmitted on rcom_tx output signal using Manchester encoding(for 1-->10, 0-->01). 32-bit hex word in Binary forma is

b^0001_0000_0000_0000_0001_0000_0000_0000
Now the manchester form is(MSB-->LSB):
01010110_01010101_01010101_01010101_10010101_01010101_01010101_01010101
for every bit of manchester there is 50 ns +/- 15 ns delay
so what i am writing as my concepts of VHDL: For MSB(01010110)
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
----------------------------------------------
Here i need confirmation that: Is there any other easy way of writing
this data on rcom_tx with delay. And also suggest how to represent the
tolerance value with this.

Please give me suggestions
Sreeniv

u can store the value in a variable and shift it every 50 ns using a
FOR loop.

 

[backhus]

Hi all,
I need some suggestion on writing testbench of non-systhesizable code
I have 32-bit hex word; for example: 0x1000 1000 and this should be
transmitted on rcom_tx output signal using Manchester encoding(for 1-->10, 0-->01). 32-bit hex word in Binary forma is

b^0001_0000_0000_0000_0001_0000_0000_0000
Now the manchester form is(MSB-->LSB):
01010110_01010101_01010101_01010101_10010101_01010101_01010101_01010101
for every bit of manchester there is 50 ns +/- 15 ns delay
so what i am writing as my concepts of VHDL: For MSB(01010110)
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='1';
wait for 50 ns; rcom_tx<='0';
----------------------------------------------
Here i need confirmation that: Is there any other easy way of writing
this data on rcom_tx with delay. And also suggest how to represent the
tolerance value with this.

Please give me suggestions
Sreeniv

Hi Sreeniv,
as said before, a loop is a good idea.

Another, but not so good, possibility is the after statement:

rcom_tx <= 0,
1 after 50 ns,
1 after 100 ns,
1 after 150 ns,
1 after 200 ns,
1 after 250 ns,
1 after 300 ns,
1 after 350 ns;

To model your jitter you can use ( 35 ns + tx_jitter).
Where txjitter is a value between 0 and 30 ns that has to be
calculated somehow.
Pseudo random noise sequences are a good choice. (made with simple
shift registers (LFSRs)).
They produce always the same sequence, so your tests can be verified
anytime with the same stimuli.
And with a simple seed value you can change the behavior in a
controlled manner.

Have a nice simulation
Eilert

 

[Andy]

Purely personal preference, but I might make random_delay() be a
function that returns the time value to wait: "wait for random_delay
(...);". Might be more reusable elsewhere, and/or useable with a
delayed assignment. Again, just one POV.

Note also that Bromley's approach to indexing the array is more
efficient in a testbench than shifting the data as suggested earlier
by Shanmugavel.

Testbench efficiency (simulation speed) is often very different from
synthesized hardware efficiency. Accordingly, indexing the array in HW
would be much less efficient than a shift register.

Andy

 

[JSreeniv]

I disagree.  Managing the result of an LFSR to get useful
random numbers is messy and non-trivial.  Surely it's far
easier to use ieee.math_real.uniform() in a testbench?


That's true for uniform() also.

...
use ieee.math_real.all;
...
...
  constant START_SEED: positive := 42;  -- or whatever
  ...
begin
  ...
  process bitstream_generator;
    variable seed1, seed2: positive := START_SEED;
    procedure random_delay(min, max: time) is
      variable random_real: real;
    begin
      -- Delay for randomized time, average (min+max)/2
      uniform(seed1, seed2, random_real);
      wait for min + (max-min) * random_real;
    end;
  begin
    for i in stimulus_vector'range loop -- MSB downto LSB
      -- Put out one data bit on to the line
      serial_line <= stimulus_vector(i);
      random_delay(35 ns, 65 ns);
    end loop;
    ...

This is only a sketch - there's much more you can do,
of course.

Enjoy.
--
Jonathan Bromley, Consultant

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Hi Bromley,

Thanks for your response,
could you please elaborate more about this issue
where i have 29 data words of each 32-bit, and anytime i can sent any
number of data's..so this is the complexity i am getting confuse. My
data each time is only in Hexadecimal format and what i done is i
wrote a package to convert hex to binary and then binary to Manchester
encoding with including the wait time 50 ns for every bit of encoded
data but its not working. I done using two procedures in a package and
felt its not very efficient way..so could please give some suggestion
on this..to how to proceed.

thanks