Array of generic width std_logic_vector in entity?

Discussion in 'VHDL' started by Brandon, Jul 13, 2005.

  1. Brandon

    Brandon Guest

    >From reading old posts, I see it is not possible to have an array of
    generic-width std_logic_vector in an entity. I've seen some of the work
    arounds, including using the type std_logic_matrix, but I'm not
    entirely happy with them (none of them are straightforward).

    Are there any plans to allow unconstrained arrays to have unconstrained
    elements? Something like...

    type arrayofstdlv_t is array (natural range<>) of std_logic_vector;

    Such that, I could have an entity like,

    entity myentity is
    generic (
    depth: integer;
    width: integer
    port (
    x : in arrayofstdlv_t(depth-1 downto 0)(width-1 downto 0);
    ...
    );
    end entity myentity;

    I'm trying to implement something like this now, and I really don't
    want to unwrap a generic array of std_logic_vector's to one long
    generic depth*width length vector to implement it.

    What does everyone else do in practice for writing generic models?
     
    Brandon, Jul 13, 2005
    #1
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  2. Brandon wrote:

    >>From reading old posts, I see it is not possible to have an array of

    > generic-width std_logic_vector in an entity. I've seen some of the work
    > arounds, including using the type std_logic_matrix, but I'm not
    > entirely happy with them (none of them are straightforward).


    > entity myentity is
    > generic (
    > depth: integer;
    > width: integer
    > port (
    > x : in arrayofstdlv_t(depth-1 downto 0)(width-1 downto 0);
    > ...
    > );
    > end entity myentity;


    Remember, that some old synthesis tools are not capable of synthesizing
    2D-arrays!

    Every x-dimensional array can be broken down into a (x-1)-dimensional
    array until you have reached the 1D-array.
    Example: The 2D-array

    1,2,3,4
    5,6,7,8
    a,b,c,d

    can also be written as the 1D-array

    1,2,3,4,5,6,7,8,a,b,c,d

    Therefore it is always possible to break arrays in entities down to
    1D-arrays (vectors).


    Ralf
     
    Ralf Hildebrandt, Jul 13, 2005
    #2
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  3. Brandon

    Brandon Guest

    I'm not worried about using old synthesis tools...

    Yes, I understand this is possible, but it's not as clean as I would
    like. In a simulation environment a long vector like that doesn't
    convey any information in a straightforward way. For example, I might
    have an array of length 32 of std_logic_vector(15 downto 0) for a total
    of 512 bits, which represent 32 numeric inputs. In a testbench I
    typically display these ports in hex and if they are fixed-point
    numbers, I'll have a conversion entity to translate that fixed-point
    number to floating point for visual inspection and verification.

    But like I said, I can't create an array of unconstrained vectors,
    which I find to be somewhat limiting. Is the 1-d vector technique the
    typical workaround? In the end we're still talking the same number of
    bits, it's just the syntax of the model in question.
     
    Brandon, Jul 18, 2005
    #3
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