array of STD_LOGIC to STD_LOGIC_VECTOR

Discussion in 'VHDL' started by poulette, Feb 12, 2009.

  1. poulette

    poulette

    Joined:
    Feb 12, 2009
    Messages:
    1
    Hi,
    I would like to know if there is a way to put a signal STD_LOGIC_VECTOR in an array of STD_LOGIC ??

    Ex :

    type X is array(7 downto 0) of STD_LOGIC;
    signal Y : X;

    signal A : STD_LOGIC_VECTOR(7 downto 0);

    ...

    A <= Y; -- ou bien Y <= A;

    thank you
     
    poulette, Feb 12, 2009
    #1
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  2. poulette

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Not clue why you're defining your own std_logic_vector equivalent, but in VHDL the types are incompatible. You will have to assign element-wise like this,

    copy: for i in X'range generate
    A(i) <= Y(i);
    Y(i) <= B(i);
    end generate copy;
     
    joris, Feb 12, 2009
    #2
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