Array rotate : "Range bound must be a constant" in synthesis

Discussion in 'VHDL' started by Pasacco, Oct 29, 2006.

  1. Pasacco

    Pasacco Guest

    Hello

    I have one error message "Range bound must be a constant" duriung
    synthesis.


    I intend to rotate a variable sized integer array.
    Array looks like {size, element,..,element }.
    Number of elements = size.
    I wish to get new array, rotated by "pos" value.


    For example,
    old array = { 4, 2, 3, 1, 4} and pos = 2
    new array = { 4, 3, 1, 4, 2}.


    Another example,
    old array = { 5, 4, 2, 1, 3, 5 } and pos = 3
    new array = { 5, 1, 3, 5, 4, 2 }


    In order to implement that, I used "function", as shown in the
    following.


    1. I considered record type "parameters"


    ---- parameter to pass
    type para is array (0 to size) of integer range 0 to size;
    type parameters is record
    old : para; -- old array
    pos : integer range 0 to size; -- pos
    end record;


    2. I wrote a function below.


    The code is not synthesizable.
    Does anyone have idea how to make this synthesizable?
    Thankyou.


    -- generate new array from old array
    function NEW_ARRAY( Temp: parameters ) return para is
    variable array_out : para; -- new array
    variable CTRL : integer range 0 to size; -- pos
    variable IDX : integer range 0 to size; -- size
    begin


    CTRL := Temp.pos ;
    IDX := Temp.old(0);


    array_out(0) := Temp.old(0);


    if ( IDX = 0 or CTRL = 0 ) then array_out := (others => 0 );
    else


    for I in CTRL to IDX loop
    array_out(I - CTRL + 1) := Temp.old(I); ---- problematic
    end loop;


    for I in 1 to CTRL-1 loop
    array_out(I + IDX - CTRL + 1) := Temp.old(I); ---- problematic
    end loop;


    end if;
    return array_out;
    end NEW_ARRAY;
    Pasacco, Oct 29, 2006
    #1
    1. Advertising

  2. Pasacco wrote:

    > I have one error message "Range bound must be a constant" duriung
    > synthesis.

    ....
    > 2. I wrote a function below.

    ....
    > The code is not synthesizable.
    > Does anyone have idea how to make this synthesizable?


    Synthesis infers logic between
    entity input and output ports only.

    Functions may be used to describe values,
    which indirectly infer hardware, but
    an entity and architecture are also
    needed to describe assignments
    to the output ports.

    See how the functions
    rising_edge and bit_done
    are used in the reference design here:

    http://home.comcast.net/~mike_treseler/


    -- Mike Treseler
    Mike Treseler, Oct 29, 2006
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    4
    Views:
    2,071
    Ralf Hildebrandt
    Sep 8, 2003
  2. walala
    Replies:
    4
    Views:
    1,170
    Technology Consultant
    Sep 9, 2003
  3. RC
    Replies:
    1
    Views:
    848
    Bjoern Hoehrmann
    Aug 3, 2006
  4. Pasacco
    Replies:
    0
    Views:
    603
    Pasacco
    Oct 29, 2006
  5. IanJSparks
    Replies:
    0
    Views:
    1,120
    IanJSparks
    Jan 10, 2008
Loading...

Share This Page