ASIC and FPGA : inferring multiplier

Discussion in 'VHDL' started by Pasacco, Jun 3, 2008.

  1. Pasacco

    Pasacco Guest

    I hope this general discussion is scope of this group.

    In my experience, when we describe in VHDL:

    c = a * b;

    In FPGA design flow, multiplier is automatically "inferred",

    while (after synthesis) we can know "what multiplier (for example,
    booth multiplier)" and "how many multipliers" are instantiated.

    As ASIC novice, today I tried ASIC flow (using Synopsys design
    compiler).

    After synthesis, netlist SEEMS to be correctly generated.

    while I have no idea "what multiplier" and "how many multipliers" are
    correctly inferred.

    My question is that

    1) In typical ASIC flow, should I build the multiplier module MYSELF?

    2) How can we know "what multiplier" and "how good the inferred
    multiplier" are ?
     
    Pasacco, Jun 3, 2008
    #1
    1. Advertising

  2. Pasacco

    HT-Lab Guest

    "Pasacco" <> wrote in message
    news:...
    >I hope this general discussion is scope of this group.
    >
    > In my experience, when we describe in VHDL:
    >
    > c = a * b;
    >
    > In FPGA design flow, multiplier is automatically "inferred",
    >
    > while (after synthesis) we can know "what multiplier (for example,
    > booth multiplier)" and "how many multipliers" are instantiated.
    >
    > As ASIC novice, today I tried ASIC flow (using Synopsys design
    > compiler).
    >
    > After synthesis, netlist SEEMS to be correctly generated.
    >
    > while I have no idea "what multiplier" and "how many multipliers" are
    > correctly inferred.
    >
    > My question is that
    >
    > 1) In typical ASIC flow, should I build the multiplier module MYSELF?


    You can build it yourself or instantiate one from the Synopsys Designware
    library.

    >
    > 2) How can we know "what multiplier" and "how good the inferred
    > multiplier" are ?


    Without specifying one I suspect that your multiplier is a black box, speak
    to your Synopsys FAE,

    Hans
    www.ht-lab.com
     
    HT-Lab, Jun 3, 2008
    #2
    1. Advertising

  3. Pasacco

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    1) In typical ASIC flow, should I build the multiplier module MYSELF?

    2) How can we know "what multiplier" and "how good the inferred
    multiplier" are ?


    Hi

    1)
    A interfered multiplier will always depend on the type of FPGA your using - XiLinx Spartan 3 would give you 18x18bit=36bit multipliers.
    No your dont have to but if can you get some hints here:
    http://www.jjmk.dk/MMMI/Lessons/06_Arithmetics/No3_Multipliers/Index.htm

    2)
    By setting up userconstrains should it be possible to "select" any of the internal multipliers - but it will normally be better if you let the tools do the selection.

    Jeppe
     
    jeppe, Jun 3, 2008
    #3
  4. Pasacco wrote:

    > As ASIC novice, today I tried ASIC flow (using Synopsys design
    > compiler).
    >
    > After synthesis, netlist SEEMS to be correctly generated.
    >
    > while I have no idea "what multiplier" and "how many multipliers" are
    > correctly inferred.


    The selections that DC made are in the synthesis logs.


    > My question is that
    >
    > 1) In typical ASIC flow, should I build the multiplier module MYSELF?


    Usually not, unless you really know what you are doing. The synthesizer
    will build a good multiplier if you have the needed licenses.

    > 2) How can we know "what multiplier" and "how good the inferred
    > multiplier" are ?


    What you need is Designware library on top of DC. DC alone can't do good
    arithmetic blocks without DW. When DW is enabled in the flow your
    synthesis constraints help DC to choose correct multiplier or
    you can also force what multiplier architecture is used (see
    the manuals).

    --Kim
     
    Kim Enkovaara, Jun 4, 2008
    #4
  5. Pasacco

    Pasacco Guest

    In the log file,

    Processing 'TOP_DW01_add_0'
    Processing 'TOP_DW01_add_1'
    Processing 'TOP_DW02_mult_0'
    Processing 'TOP_DW01_add_2'
    Processing 'TOP_DW01_sub_0'
    Processing 'TOP_DW02_mult_1'

    Some adders and multipliers are inferred.
    The design is 120 MHz in FPGA and 450MHz in ASIC.
    So, it seems the flow is okay. thank you very much for reply.
     
    Pasacco, Jun 5, 2008
    #5
  6. Pasacco wrote:
    > In the log file,
    >
    >..
    > Processing 'TOP_DW02_mult_0'
    >...
    > Some adders and multipliers are inferred.
    > The design is 120 MHz in FPGA and 450MHz in ASIC.
    > So, it seems the flow is okay. thank you very much for reply.


    You should also see somewhere what multiplier architecture was
    really selected. If DC+DW are recent versions it should be
    either csa (Cassy-Save array) that does not need DW license
    or pparch (Delay-optimized Booth Wallace) which needs DW
    license.

    You need something like this for DW in the synthesis scripts

    set synthetic_library [list dw_foundation.sldb]
    set link_library [concat $target_library $synthetic_library]
    set search_path [concat $search_path [list \
    [format “%s%s” $synopsys_root “/dw/sim_ver”]]]
    set synlib_wait_for_design_license [list “DesignWare”]

    and to force faster multiplier (if the constraints are not
    finished) something like this.

    set_implementation pparch [list my_multiplier]


    There are also many different adder architectures available
    (rpl,cla,pparch,clf,bk,csm,rpcs at least). So the frequency
    you achieved could be much higer with some synthesis script
    changes.

    --Kim
     
    Kim Enkovaara, Jun 6, 2008
    #6
  7. Pasacco

    Pasacco Guest

    Hello Kim, I have problem to use components in the design ware.
    Let me ask one question :)

    I wish to use the "DW_sqrt_pipe" component (square root).

    In my VHDL, I simply instantiated the component:
    --------------------------------------
    .....
    U1 : DW_sqrt_pipe
    generic map (width => 32,
    tc_mode => 0,
    num_stages => 2,
    stall_mode => 1,
    rst_mode => 1 )
    port map (clk => clock,
    rst_n => reset,
    en => en,
    a => a1,
    root => root1 );
    --------------------------------------

    The synthesis log contains warning:
    --------------------------------------
    Warning: Can't find the design 'DW_sqrt_pipe'
    in the library 'WORK'. (LBR-1)
    Warning: Unable to resolve reference 'DW_sqrt_pipe' in 'TOP'. (LINK-5)
    --------------------------------------

    It seems that the library "DW_sqrt_pipe" is not compiled into WORK.

    My script is following:
    --------------------------------------
    set synthetic_library /cad/synopsys/libraries/syn/dw_foundation.sldb
    set target_library /opt/data/Syn_libs/tcbn90gthptc.db
    set link_library /opt/data/Syn_libs/tcbn90gthptc.db
    analyze -format vhdl {SQ.vhd}
    elaborate TOP
    ......
    --------------------------------------

    I can not modify .dc_synopsys.setup file and .cshrc file.
    Could you please guide me what needs to be modified in the script?
    Thnak you in advance.
     
    Pasacco, Jun 6, 2008
    #7
  8. Pasacco wrote:

    > Could you please guide me what needs to be modified in the script?
    > Thnak you in advance.


    You could copy settings that were in my last mail, that example was from
    DW documentation. I think you need dw also in the link library setting.
    It has been a while since I used DC, one option would be also to use
    the DC reference flow scripts that can be downloaded from the solvnet.
    It has all the bells and whistles in place for different DC versions.

    --Kim
     
    Kim Enkovaara, Jun 9, 2008
    #8
  9. Pasacco

    Pasacco Guest

    hi Kim. i will investigate. thank you for reply.
     
    Pasacco, Jun 9, 2008
    #9
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Anand P Paralkar

    ASIC RTL and FPGA RTL

    Anand P Paralkar, Apr 26, 2004, in forum: VHDL
    Replies:
    1
    Views:
    4,869
    Alexander Gnusin
    Apr 26, 2004
  2. Oleg
    Replies:
    1
    Views:
    625
    Mike Treseler
    Jul 6, 2004
  3. Neo

    ASIC to FPGA??

    Neo, Feb 1, 2005, in forum: VHDL
    Replies:
    0
    Views:
    575
  4. Replies:
    4
    Views:
    3,022
    Weng Tianxiang
    Jun 6, 2005
  5. ted
    Replies:
    1
    Views:
    474
    airol
    Aug 17, 2007
Loading...

Share This Page