ASIC RTL and FPGA RTL

Discussion in 'VHDL' started by Anand P Paralkar, Apr 26, 2004.

  1. Hi,

    I was talking to an "expert" in synthesis and he mentioned that there is
    a lot of difference between a synthesizable RTL code for a FPGA and a
    synthesizable RTL code for an ASIC.

    Is this true?

    If so, could you please point the significant differences between the
    two and what causes these differences.

    Thanks,
    Anand
     
    Anand P Paralkar, Apr 26, 2004
    #1
    1. Advertising

  2. Alexander Gnusin, Apr 26, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Oleg
    Replies:
    1
    Views:
    625
    Mike Treseler
    Jul 6, 2004
  2. Neo

    ASIC to FPGA??

    Neo, Feb 1, 2005, in forum: VHDL
    Replies:
    0
    Views:
    575
  3. Replies:
    4
    Views:
    3,022
    Weng Tianxiang
    Jun 6, 2005
  4. ted
    Replies:
    1
    Views:
    474
    airol
    Aug 17, 2007
  5. Pasacco
    Replies:
    8
    Views:
    1,656
    Pasacco
    Jun 9, 2008
Loading...

Share This Page