Aside from delta cycles and/or resolution functions, how can the effective value of a signal differ

Discussion in 'VHDL' started by Colin Paul Gloster, Jan 11, 2007.

  1. From Chapter 12 Elaboration and execution of the VHDL93 and VHDL2006 standards:


    [..] The driving value of a given signal is the value that signal
    provides as a source of other signals. The effective
    value of a given signal is the value obtainable by evaluating a
    reference to the signal within an expression. The driving
    value and the effective value of a signal are not always the same,
    especially when resolution functions and conversion
    functions or type conversions are involved in the propagation of
    signal values.


    I wish to understand how the effective value can differ from a driving
    value of its. I already understand a number of circumstances in which
    this can happen...

    Though it is written that "especially" resolution functions and
    conversions are relevant to an effective value not being the same as a
    driving value, I consider delta cycles to be relevant most often,
    e.g. ...

    entity studying_effective_and_driving_values is
    end studying_effective_and_driving_values;

    architecture delta_example of studying_effective_and_driving_values is
    signal D : integer := 100;
    D <= -D;

    I do not dismiss resolution functions as being irrelevant to this
    topic, e.g. ...

    library IEEE;
    use IEEE.std_logic_1164.all;

    architecture multiple_drivers_example of
    studying_effective_and_driving_values is
    signal Source1 : std_logic := '1';
    signal Source2 : std_logic := '1';
    signal Source3 : std_logic := '1';
    signal Source4 : std_logic := '0';
    signal Target : std_logic;
    Target <= Source1;
    Target <= Source2;
    Target <= Source3;
    Target <= Source4;

    I am unsure of how else the effective value of a signal is not
    identical to a driving value of that signal so I would like
    clarification and examples, please. I understand that converting a
    value of one type to another type can produce a different value
    (e.g. due to rounding), but in such a circumstance whose result is
    assigned to a signal, which of the value undergoing conversion and the
    value resulting from conversion is this statement's driving value?
    Would this possibly be an example of a cause of a driving value not
    being the same as the effective value?

    In VHDL, a so-called conversion function or type conversion can be
    invoked even when only strictly one type is involved. Is it possible
    that in such a circumstance, that this would cause a driving value to not
    be the same as the effective value (even if the conversion function
    does nothing except return its parameter)?

    Aside from the possible possibilities mentioned above, how can a
    conversion function or type conversion cause a driving value to not be
    the same as the effective value?

    I do not interpret the word "especially" in Chapter 12 as a hint that
    the list is exhaustive. How else can a driving value not be the same
    as the effective value?

    Is support, or lack thereof, for these situations uniform across
    synthesis tools? Which of these situations, if any, are not supported
    by a synthesis tool?

    Thank you for your attention,
    Colin Paul Gloster
    Colin Paul Gloster, Jan 11, 2007
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