assert false report "blah blah blah" severity note;

Discussion in 'VHDL' started by A. Kong, Oct 11, 2004.

  1. A. Kong

    A. Kong Guest

    Hi, all,

    I want to use the statment " assert false report "blah blah blah"
    severity note;" as a way to print some information in ModelSim. However,
    Xilinx, upon compiling the source, says:

    Assertion st
    atement ignored.


    My questions are:
    1) Is there any restriction on how to use assert statement? e.g. cannot
    be used in process? if loop? Or is it just Xilinx?
    2) Is there a better to print debug info? Utlimately I want to examine
    the content of a region of memory...

    Maybe I am not reading carefully but vhdl cookbook seems to only only
    provide description of usage of assert.


    Cheers,
    Anthony
     
    A. Kong, Oct 11, 2004
    #1
    1. Advertisements

  2. Hi,

    "A. Kong" <ahwkong2x1000-at-anti-spam-yahoo.com> wrote in message
    news:416a2152$...
    > Hi, all,
    >
    > I want to use the statment " assert false report "blah blah blah"
    > severity note;" as a way to print some information in ModelSim. However,
    > Xilinx, upon compiling the source, says:
    >
    > Assertion st
    > atement ignored.
    >


    Assert stuff is meant for simulation only and hence during synthesis it is
    ignored.

    >
    > My questions are:
    > 1) Is there any restriction on how to use assert statement? e.g. cannot
    > be used in process? if loop? Or is it just Xilinx?


    I would say any synthesis tool.

    >2) Is there a better to print debug info? Utlimately I want to examine
    >the content of a region of memory...


    You may want to try:

    http://www.easics.com/webtools/freesics/PCK_FIO-2002.7

    They have a neat printf like package. Also a google search for "printf vhdl
    package" yielded: http://bear.ces.cwru.edu/vhdl/source/debugio_h.vhd

    HTH,
    Srinivasan
    --
    Srinivasan Venkataramanan
    Corp. Appl. Engineer
    Synopsys India Pvt. Ltd.
    Bangalore, India
    email:synopsys.com@svenkat
    I own my words and not my employer, unless specifically mentioned
     
    Srinivasan Venkataramanan, Oct 11, 2004
    #2
    1. Advertisements

  3. A. Kong

    Iwo Mergler Guest

    A. Kong wrote:
    > Hi, all,
    >
    > I want to use the statment " assert false report "blah blah blah"
    > severity note;" as a way to print some information in ModelSim. However,
    > Xilinx, upon compiling the source, says:
    >
    > Assertion st
    > atement ignored.
    >
    >
    > My questions are:
    > 1) Is there any restriction on how to use assert statement? e.g. cannot
    > be used in process? if loop? Or is it just Xilinx?
    > 2) Is there a better to print debug info? Utlimately I want to examine
    > the content of a region of memory...
    >
    > Maybe I am not reading carefully but vhdl cookbook seems to only only
    > provide description of usage of assert.
    >
    >
    > Cheers,
    > Anthony


    If you just want to output a string in the simulator, use
    report "Whatever" severity note. The assert is not necessary.
    It should work for simulation. If you synthesize the design,
    it gets indeed ignored.

    Kind regards,

    Iwo
     
    Iwo Mergler, Oct 11, 2004
    #3
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. evolve
    Replies:
    2
    Views:
    675
    William Ryan
    Nov 2, 2003
  2. Hylander
    Replies:
    0
    Views:
    531
    Hylander
    Jan 16, 2004
  3. Robert Brewer
    Replies:
    1
    Views:
    702
    bsmith
    Nov 7, 2004
  4. Thomas Guettler

    assert 0, "foo" vs. assert(0, "foo")

    Thomas Guettler, Feb 23, 2005, in forum: Python
    Replies:
    3
    Views:
    2,755
    Carl Banks
    Feb 23, 2005
  5. boney
    Replies:
    1
    Views:
    362
    Graham Dumpleton
    Nov 14, 2006
  6. Alex Vinokur

    assert(x) and '#define ASSERT(x) assert(x)'

    Alex Vinokur, Nov 25, 2004, in forum: C Programming
    Replies:
    5
    Views:
    1,166
    Keith Thompson
    Nov 25, 2004
  7. Prashant
    Replies:
    0
    Views:
    842
    Prashant
    Apr 10, 2008
  8. ImpalerCore

    To assert or not to assert...

    ImpalerCore, Apr 27, 2010, in forum: C Programming
    Replies:
    79
    Views:
    2,373
    Richard Bos
    May 17, 2010
Loading...