assert false report "blah blah blah" severity note;

Discussion in 'VHDL' started by A. Kong, Oct 11, 2004.

  1. A. Kong

    A. Kong Guest

    Hi, all,

    I want to use the statment " assert false report "blah blah blah"
    severity note;" as a way to print some information in ModelSim. However,
    Xilinx, upon compiling the source, says:

    Assertion st
    atement ignored.


    My questions are:
    1) Is there any restriction on how to use assert statement? e.g. cannot
    be used in process? if loop? Or is it just Xilinx?
    2) Is there a better to print debug info? Utlimately I want to examine
    the content of a region of memory...

    Maybe I am not reading carefully but vhdl cookbook seems to only only
    provide description of usage of assert.


    Cheers,
    Anthony
     
    A. Kong, Oct 11, 2004
    #1
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  2. Hi,

    "A. Kong" <ahwkong2x1000-at-anti-spam-yahoo.com> wrote in message
    news:416a2152$...
    > Hi, all,
    >
    > I want to use the statment " assert false report "blah blah blah"
    > severity note;" as a way to print some information in ModelSim. However,
    > Xilinx, upon compiling the source, says:
    >
    > Assertion st
    > atement ignored.
    >


    Assert stuff is meant for simulation only and hence during synthesis it is
    ignored.

    >
    > My questions are:
    > 1) Is there any restriction on how to use assert statement? e.g. cannot
    > be used in process? if loop? Or is it just Xilinx?


    I would say any synthesis tool.

    >2) Is there a better to print debug info? Utlimately I want to examine
    >the content of a region of memory...


    You may want to try:

    http://www.easics.com/webtools/freesics/PCK_FIO-2002.7

    They have a neat printf like package. Also a google search for "printf vhdl
    package" yielded: http://bear.ces.cwru.edu/vhdl/source/debugio_h.vhd

    HTH,
    Srinivasan
    --
    Srinivasan Venkataramanan
    Corp. Appl. Engineer
    Synopsys India Pvt. Ltd.
    Bangalore, India
    email:synopsys.com@svenkat
    I own my words and not my employer, unless specifically mentioned
     
    Srinivasan Venkataramanan, Oct 11, 2004
    #2
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  3. A. Kong

    Iwo Mergler Guest

    A. Kong wrote:
    > Hi, all,
    >
    > I want to use the statment " assert false report "blah blah blah"
    > severity note;" as a way to print some information in ModelSim. However,
    > Xilinx, upon compiling the source, says:
    >
    > Assertion st
    > atement ignored.
    >
    >
    > My questions are:
    > 1) Is there any restriction on how to use assert statement? e.g. cannot
    > be used in process? if loop? Or is it just Xilinx?
    > 2) Is there a better to print debug info? Utlimately I want to examine
    > the content of a region of memory...
    >
    > Maybe I am not reading carefully but vhdl cookbook seems to only only
    > provide description of usage of assert.
    >
    >
    > Cheers,
    > Anthony


    If you just want to output a string in the simulator, use
    report "Whatever" severity note. The assert is not necessary.
    It should work for simulation. If you synthesize the design,
    it gets indeed ignored.

    Kind regards,

    Iwo
     
    Iwo Mergler, Oct 11, 2004
    #3
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