Assertions

Discussion in 'VHDL' started by thunder, Jul 22, 2011.

  1. thunder

    thunder Guest

    Hello

    We do our development work in VHDL.

    We are starting to formulate our ABV strategy and are currently
    thinking of using PSL assertions to either imbed in the VHDL code or
    define the PSL assertions as vunits.

    However, another line of thought is to use System Verilog assertions
    with the VHDL RTL, since later on we want to go down the UVM strategy
    and Random Constrained Verification.


    QS: Does anyone have any feel for
    1) how easy/difficult it is to connect the System Verilog
    assertions to the VHDL RTL?
    2) How easy/difficult it will be to debug the assertions if
    we adopt the System Verilog assertions and VHDL?


    Thanks

    J
     
    thunder, Jul 22, 2011
    #1
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  2. thunder

    HT-Lab Guest

    On 22/07/2011 12:21, thunder wrote:
    > Hello
    >
    > We do our development work in VHDL.
    >


    Good!

    > We are starting to formulate our ABV strategy and are currently
    > thinking of using PSL assertions to either imbed in the VHDL code or
    > define the PSL assertions as vunits.


    You will probably use both.

    >
    > However, another line of thought is to use System Verilog assertions
    > with the VHDL RTL, since later on we want to go down the UVM strategy


    I wouldn't worry to much, there is quite some similarity between PSL and
    SVA as both standards are maintained/developed by Accellera.

    If you use VHDL then I would suggest you stick with PSL. You will learn
    it quicker than SVA as you can use familiar operators and constructs
    (AND, OR, is, to, rising_edge etc).

    I also believe IMHO that PSL is easier to learn than SVA.

    The disadvantage of PSL (as is with VHDL) is that EDA vendors seem to
    spend their R&D budget on SV and SVA only. This is not because these
    languages are superior but simply because of the 20/80 rule (80% of
    their revenue comes from 20% of their customers and these 20% are all
    big Verilog/SV ASIC users).

    For PSL you also need to use a bit of extra code as bins and related
    verification constructs are not part of the standard.

    > and Random Constrained Verification.


    You can do CR with VHDL as well. Jim Lewis has a great CR package on his
    website. What is lacking is support for a constraint solver but you
    should be able to cook something up using the FLI/VHPI.

    >
    > QS: Does anyone have any feel for
    > 1) how easy/difficult it is to connect the System Verilog
    > assertions to the VHDL RTL?


    Not difficult, you simply "bind" the SVA module to your VHDL
    entity/architecture. Note that SVA does not support embedded assertions.

    > 2) How easy/difficult it will be to debug the assertions if
    > we adopt the System Verilog assertions and VHDL?


    It depends on your simulator but I suspect no different from debugging PSL.

    Good luck,

    Hans
    www.ht-lab.com


    >
    >
    > Thanks
    >
    > J
     
    HT-Lab, Jul 22, 2011
    #2
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  3. thunder

    JimLewis Guest

    Hi,
    > We do our development work in VHDL.
    >
    > We are starting to formulate our ABV strategy and are currently
    > thinking of using PSL assertions to either imbed in the VHDL code or
    > define the PSL assertions as vunits.
    >
    > However, another line of thought is to use System Verilog assertions
    > with the VHDL RTL, since later on we want to go down the UVM strategy
    > and Random Constrained Verification.


    I would keep it simple. For assertions in a VHDL program, I would use
    PSL.

    Before you invest in System Verilog, you might want to take a look at:
    http://www.mentor.com/company/industry_keynotes/upload/DVCon-2011.pdf

    Their claim is that SV + UVM + CRV, but instead that you need an
    additional
    intelligent testbench tool to effectively do verification. Hence, it
    is
    a significant investment in tools.

    OTOH, in VHDL, in addition to our Randomization package that Hans
    mentioned,
    you might want to also check out our Coverage Package. The 2.1
    release
    takes you part of the way to more effective verification, however, in
    the
    next several releases (2.2 due soon), the capability is growing.
    Check it out at:
    http://www.synthworks.com/downloads/index.htm

    Best,
    Jim
     
    JimLewis, Jul 28, 2011
    #3
  4. thunder

    JimLewis Guest

    > We do our development work in VHDL.
    >
    > We are starting to formulate our ABV strategy and are currently
    > thinking of using PSL assertions to either imbed in the VHDL code or
    > define the PSL assertions as vunits.


    For VHDL, I would stick with PSL.

    > However, another line of thought is to use System Verilog assertions
    > with the VHDL RTL, since later on we want to go down the UVM strategy
    > and Random Constrained Verification.


    As an alternative to SV, check out our free open-source VHDL
    packages for functional coverage and randomization. At the
    end of the day, I think functional coverage is going to become
    more and more important. Currently our functional coverage
    methodology is setup so you can capture high-fidelity functional
    coverage models and use these go guide your randomization.

    The packages are available at:
    http://www.synthworks.com/downloads

    Best,
    Jim
     
    JimLewis, Jul 28, 2011
    #4
  5. thunder

    sri.cvcblr

    Joined:
    Aug 4, 2011
    Messages:
    2
    Location:
    Bangalore India
    To add little more to the great points made by Hans & Jim - we also recommend using PSL for VHDL designs as it is now part of VHDL-2008 standard itself, so really if you say VHDL, it has all the power of a full, temporal assertion language ( a la SVA) in it - so why bother?

    Another significant reason to use PSL (and this originated from some local VHDL customers exploring similar to the OP) - the RTL designers can also add them, and debug them etc. Since you also mentioned debug - don't discount that aspect of the flow. Especially with assertions talking about (potentially/typically) low level signal details it is highly important that you keep your designers happy with the new technology additions. Hence VHDL-08 (with PSL syntax) is THE way to go for adding assertions to VHDL designs.

    Having said that, in case you want to connect SV to VHDL, all the major EDA vendors (SNPS, MENT, CDN, Aldec) allow:

    1. SV Interface - VHDL RTL
    2. SVA bind to VHDL RTL

    HTH
    Srini
    www.cvcblr.com/blog
     
    sri.cvcblr, Aug 4, 2011
    #5
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