In addition to the Alexander suggestion, there is also one
other variable to setup in your ".synopsys_dc_setup" :
verilogout_no_tri = "true"
write_name_nets_same_as_ports = "true"
And also a command to be setup just before the optimization
step :
set_fix_multiple_port_nets -all
Unfortunately this last command cannot be set as a global
variable, you have to activate it on the module you are
optimizing and this should be done just before launching
the optimization.
Long time ago Synopsys have had a better way to do this by a
global variable, but this is not the case for the recent
versions of Design Compiler.
On the other hand, I would recommand you to execute the
"change_names" command before writting your Verilog or VHDL
netlist, respectively by the 2 commands below :
change_names -rules verilog -hierarchy -verbose > change_names.v
change_names -rules vhdl -hierarchy -verbose > change_names.vhd
Hope this helps.
Regards,
=================
Kholdoun TORKI
http://cmp.imag.fr
==================