assign statement verilog

Discussion in 'VHDL' started by Jerrie85, Aug 18, 2006.

  1. Jerrie85

    Jerrie85

    Joined:
    Aug 18, 2006
    Messages:
    7
    Hello folks,
    this is most prob a newb question, but in vhdl, i can assign values to vectors like,


    valueout <= value1 when addr=addr2 else
    value3 when addr=add3 else
    value 4;

    how can i do this same thing in verilog? i have searched everywhere, and i have found nonething to aid me
    Jerrie85, Aug 18, 2006
    #1
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