Hello folks,
this is most prob a newb question, but in vhdl, i can assign values to vectors like,
valueout <= value1 when addr=addr2 else
value3 when addr=add3 else
value 4;
how can i do this same thing in verilog? i have searched everywhere, and i have found nonething to aid me
this is most prob a newb question, but in vhdl, i can assign values to vectors like,
valueout <= value1 when addr=addr2 else
value3 when addr=add3 else
value 4;
how can i do this same thing in verilog? i have searched everywhere, and i have found nonething to aid me