assigning output to input

Discussion in 'VHDL' started by Simone Winkler, Aug 28, 2003.

  1. Hello!

    I tried to do a RS-flip-flop with nor-gates in VHDL. But i got the following
    error message:

    Parameter notq of mode out can not be associated with a f
    ormal parameter of mode in.


    the vhdl code was:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity rs is
    Port ( S : in std_logic;
    R : in std_logic;
    Q : out std_logic;
    notQ : out std_logic);
    end rs;

    architecture Behavioral of rs is

    begin
    Q <= S nor notQ;
    notQ <= R nor Q;
    end Behavioral;


    ....it was just to try the functionality of vhdl......
    what can i do to solve this problem?

    thanx...
     
    Simone Winkler, Aug 28, 2003
    #1
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  2. "Simone Winkler" <> wrote in
    message news:...

    > I tried to do a RS-flip-flop with nor-gates in VHDL. But i got the

    following
    > error message:
    >
    > Parameter notq of mode out can not be associated with a f
    > ormal parameter of mode in.


    Sounds like you may have two problems.

    First, your code is trying to use the value of an "out" port,
    which is illegal in VHDL. You must create an internal signal, use
    that internal signal for all the useful work, and then copy it
    to the out port(s).

    Second, the error message: it sounds as if your testbench for
    this module is connecting to the ports inappropriately - or
    perhaps it's just a confusing error message.

    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;


    You don't need arithmetic packages for this code.
    Get rid of them.

    > entity rs is
    > Port ( S : in std_logic;
    > R : in std_logic;
    > Q : out std_logic;
    > notQ : out std_logic);
    > end rs;


    OK so far.

    > architecture Behavioral of rs is
    >
    > begin
    > Q <= S nor notQ; -- Can't do this (notQ is an out port)
    > notQ <= R nor Q;
    > end Behavioral;


    architecture Corrected of rs is
    signal Q_int: std_logic;
    signal Qbar_int: std_logic;
    begin
    Q_int <= S nor Qbar_int; -- this is OK
    Qbar_int <= R nor Q_int;
    -- now get the signals out to the ports:
    Q <= Q_int;
    notQ <= Qbar_int;
    end Corrected;

    > ...it was just to try the functionality of vhdl......


    OK, but be aware that combinational feedback is always a bad
    idea for synthesisable logic.
    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Aug 28, 2003
    #2
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