Assigning values to a multidimential array

Discussion in 'VHDL' started by Johnsy Joseph, Sep 20, 2004.

  1. Hello Everybody,

    I would be grateful if somebody helped me with this. I have the
    following definitions.

    type byte is array(7 downto 0) of std_logic;
    type sarray is array(6 downto 1) of byte;

    variable shift_register:sarray;
    variable shftreg_data: std_logic_vector(7 downto 0);


    I would like to do the something like this-

    shift_register(0)(7 to 0) := shftreg_data(7 to 0);

    I basically want to assign a vector to one of the elements of my array
    of vectors but it isnt working. I am using VHDL'87 but it doesnt
    compile. Any methods to do such a thing?

    Thanks for the help
    Warm Regards
    :) Johnsy
     
    Johnsy Joseph, Sep 20, 2004
    #1
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  2. Johnsy Joseph a écrit:
    > Hello Everybody,
    >
    > I would be grateful if somebody helped me with this. I have the
    > following definitions.
    >
    > type byte is array(7 downto 0) of std_logic;
    > type sarray is array(6 downto 1) of byte;
    >
    > variable shift_register:sarray;
    > variable shftreg_data: std_logic_vector(7 downto 0);
    >
    >
    > I would like to do the something like this-
    >
    > shift_register(0)(7 to 0) := shftreg_data(7 to 0);
    >
    > I basically want to assign a vector to one of the elements of my array
    > of vectors but it isnt working. I am using VHDL'87 but it doesnt
    > compile. Any methods to do such a thing?


    Hi
    VHDL is a strongly typed language. You can not assign a value to a
    signal/variable if their types don't match.
    In your example, shftreg_data is std_logic_vector and shift_register(0)
    is byte so you can't do it.
    Luckily, their types are closely related: they are made of elements of
    the same type. You can juste type cast your value:
    shift_register(0)(7 to 0) := byte(shftreg_data(7 to 0));


    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Sep 20, 2004
    #2
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  3. Some remarks:
    1. You defined a new type byte. This is not the same type as
    std_logic_vector and therefore the assignment
    shift_register(0)(7 to 0) := shftreg_data(7 to 0); has problems with
    incompatible types.
    Suggestion: use a subtype for byte:
    SUBTYPE byte IS std_logic_vector(7 downto 0);

    2. shift_register(0)(7 to 0) notice that element 0 is not in the range om 6
    downto 1 (see type declaration of sarray).

    3. you mix up "downto" and "to". If your vector is declared as a "downto"
    then a slice of that vector should also be a "downto".

    So a corrected piece of code looks like:

    subtype byte is std_logic_vector( 7 downto 0);
    type sarray is array(6 downto 0) of byte;

    variable shift_register:sarray;
    variable shftreg_data: std_logic_vector(7 downto 0);

    shift_register(0)(7 downto 0) := shftreg_data(7 downto 0);

    Egbert Molenkamp

    "Johnsy Joseph" <> schreef in bericht
    news:...
    > Hello Everybody,
    >
    > I would be grateful if somebody helped me with this. I have the
    > following definitions.
    >
    > type byte is array(7 downto 0) of std_logic;
    > type sarray is array(6 downto 1) of byte;
    >
    > variable shift_register:sarray;
    > variable shftreg_data: std_logic_vector(7 downto 0);
    >
    >
    > I would like to do the something like this-
    >
    > shift_register(0)(7 to 0) := shftreg_data(7 to 0);
    >
    > I basically want to assign a vector to one of the elements of my array
    > of vectors but it isnt working. I am using VHDL'87 but it doesnt
    > compile. Any methods to do such a thing?
    >
    > Thanks for the help
    > Warm Regards
    > :) Johnsy
     
    Egbert Molenkamp, Sep 20, 2004
    #3
  4. Thank you very much Friends !!!
    It works.

    Warm Regards
    :) Johnsy
     
    Johnsy Joseph, Sep 21, 2004
    #4
  5. Johnsy Joseph

    Jim Lewis Guest

    Going one step further from what Egbert wrote,
    you can leave off the lower level of indicies:

    shift_register(0) := shftreg_data;

    Also if your are going to define the subtype byte,
    then you ought to use it when you declare shftreg_data:
    variable shftreg_data: byte;

    Or alternately, don't use byte at all:
    type sarray is array(6 downto 0) of std_logic_vector(7 downto 0);

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


    > Some remarks:
    > 1. You defined a new type byte. This is not the same type as
    > std_logic_vector and therefore the assignment
    > shift_register(0)(7 to 0) := shftreg_data(7 to 0); has problems with
    > incompatible types.
    > Suggestion: use a subtype for byte:
    > SUBTYPE byte IS std_logic_vector(7 downto 0);
    >
    > 2. shift_register(0)(7 to 0) notice that element 0 is not in the range om 6
    > downto 1 (see type declaration of sarray).
    >
    > 3. you mix up "downto" and "to". If your vector is declared as a "downto"
    > then a slice of that vector should also be a "downto".
    >
    > So a corrected piece of code looks like:
    >
    > subtype byte is std_logic_vector( 7 downto 0);
    > type sarray is array(6 downto 0) of byte;
    >
    > variable shift_register:sarray;
    > variable shftreg_data: std_logic_vector(7 downto 0);
    >
    > shift_register(0)(7 downto 0) := shftreg_data(7 downto 0);
    >
    > Egbert Molenkamp
    >
    > "Johnsy Joseph" <> schreef in bericht
    > news:...
    >
    >>Hello Everybody,
    >>
    >>I would be grateful if somebody helped me with this. I have the
    >>following definitions.
    >>
    >>type byte is array(7 downto 0) of std_logic;
    >>type sarray is array(6 downto 1) of byte;
    >>
    >>variable shift_register:sarray;
    >>variable shftreg_data: std_logic_vector(7 downto 0);
    >>
    >>
    >>I would like to do the something like this-
    >>
    >>shift_register(0)(7 to 0) := shftreg_data(7 to 0);
    >>
    >>I basically want to assign a vector to one of the elements of my array
    >>of vectors but it isnt working. I am using VHDL'87 but it doesnt
    >>compile. Any methods to do such a thing?
    >>
    >>Thanks for the help
    >>Warm Regards
    >>:) Johnsy

    >
    >
     
    Jim Lewis, Sep 21, 2004
    #5
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