Assigning VHDL values from the command-line?

[Mark McDougall]

Hi,

I'm wondering if there's any way of passing the value of a constant to a
VHDL file from the command-line/project file under Quartus?

I have a constant in a package body that is hard-coded.
eg. constant myConstant : std_logic_vector(7 downto 0) := X"01";

What I'd _like_ to be able to do is something that is often done in
software...
eg. constant myConstant : std_logic_vector(7 downto 0) := $magic$;
....and then build with...
quartus_sh build.bat magic=2
....or there-abouts.

Is this at all possible?

I've read that you can do similar in Quartus with Verilog macros...

Regards,

 

[David R Brooks]

Hi,

I'm wondering if there's any way of passing the value of a constant to a
VHDL file from the command-line/project file under Quartus?

I have a constant in a package body that is hard-coded.
eg. constant myConstant : std_logic_vector(7 downto 0) := X"01";

What I'd _like_ to be able to do is something that is often done in
software...
eg. constant myConstant : std_logic_vector(7 downto 0) := $magic$;
....and then build with...
quartus_sh build.bat magic=2
....or there-abouts.

Is this at all possible?

I've read that you can do similar in Quartus with Verilog macros...

I don't know Quartus, but Modelsim (pretty much the standard tool) can
do this in VHDL, using generics.
Define "magic" as a generic (with a default value), then override the
default on the command line.

 

[Andy]

Hi,

I'm wondering if there's any way of passing the value of a constant to a
VHDL file from the command-line/project file under Quartus?

I have a constant in a package body that is hard-coded.
eg. constant myConstant : std_logic_vector(7 downto 0) := X"01";

What I'd _like_ to be able to do is something that is often done in
software...
eg. constant myConstant : std_logic_vector(7 downto 0) := $magic$;
...and then build with...
quartus_sh build.bat magic=2
...or there-abouts.

Is this at all possible?

I've read that you can do similar in Quartus with Verilog macros...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

I'm not aware of any tools that will let you override a constant
declaration, but many will allow you to override the default
assignment of a top level generic. In the next version of VHDL,
generics on packages are also allowed, so you could have a top level
generic on a module drive the generic assignment in the package
"instantiation".

I know most simulators, and the synplify synthesis tool allow
overriding generics via command line options.

Andy

 

[Mark McDougall]

I'm not aware of any tools that will let you override a constant
declaration, but many will allow you to override the default
assignment of a top level generic. In the next version of VHDL,
generics on packages are also allowed, so you could have a top level
generic on a module drive the generic assignment in the package
"instantiation".

Technically, I'm not 'overriding' the constant, but sucking it in from the
command-line. Regardless, it would appear I'm SOL atm...

Thanks for your input!
Regards,

 

[Tricky]

It can definately be done with generics. Ive used a TCL script to run
a test bench in all possible configurations before.