Assignment problem

Discussion in 'VHDL' started by Thomas Reinemann, Nov 10, 2004.

  1. Hello,

    I run in trouble at an assignment within a process.
    This entity is instanced twice. Within one instance T_I_reg is assigned the
    value delayed by one rising edge, as expected. But within the other
    instance the value is assigned immediately.
    I'm using Modelsim 5.8c. Further more it says that the assignment line is
    not executable.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity forwarder is

    port (
    T_I, slot_data, slot_control : in std_logic;
    reset, clk : in std_logic;
    T_O : out std_logic);

    end forwarder;


    architecture rtl of forwarder is
    signal T_I_reg : std_logic;
    begin -- rtl

    T_O <= slot_data when reset = '0' and slot_control = '1' else T_I_reg;

    forward: process (clk)
    begin -- process forward
    if rising_edge(clk) then -- rising clock edge
    T_I_reg <= T_I; -- _TROUBLE HERE_
    end if;
    end process forward;

    end rtl;


    Bye Tom.
     
    Thomas Reinemann, Nov 10, 2004
    #1
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  2. Thomas Reinemann wrote:

    > I run in trouble at an assignment within a process.
    > This entity is instanced twice. Within one instance T_I_reg is assigned the
    > value delayed by one rising edge, as expected. But within the other
    > instance the value is assigned immediately.


    What happens if you synch it up like this?

    -- T_O <= slot_data when reset = '0'
    -- and slot_control = '1' else T_I_reg;
    -- (deleted)

    forward: process (clk)
    begin -- process forward
    if rising_edge(clk) then -- rising clock edge
    if reset = '0' and slot_control = '1' then
    T_O <= slot_data;
    else
    T_I_reg <= T_I;
    end if;
    end if;
    end process forward;

    end rtl;

    -- Mike Treseler
     
    Mike Treseler, Nov 10, 2004
    #2
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