This will never be approved because it violates the basic rule of VHDL:
Readability.
You could argue that the
condition> ? <true value> : <false value> or the
<true value> ? <condition> : <false value>
syntax is "readable", but I would argue that it is more criptic.
Your argument is a little bit weak, but anyway it's not important.
I think this syntax (?: or if-else) should never be approved because we
don't want to change the existing vhdl syntax (or add new syntax to do the
same thing) but add new functionnality/flexibility.
We must keep anyway the when-else in the concurrent part for backward
compatibility. So just permit usage of the inline condionnal statement
(when-else) everywhere to simplify the number of keyword/syntax to parse.
see bellow for other comments.
In fact, when I don't use Verilog for a long time, I always find myself
referring the
syntax (I use Sutherland notes
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html)
Any language that you didn't use for a long time, vhdl included, you need a
syntax reference.
For vhdl 200x we could permit everywhere too:
if then-elsif then-else-end if
case-when-end case
for loop-end loop
An if <condition> then with a constant condition is equivalent to if
<condition> generate. So by permitting the use of if then-elsif
then-else-end if everywhere, we don't need to create an elsif generate and
else generate.
Same thing for case, no need for a case generate
for loop can replace the for generate just to simplify the language for the
new users (only one syntax to remember).
Inside a process and outside a process, we should use the same syntax to do
the same (equivalent) thing. Keep it simple. For a parser (syntax checking)
it's easier. VHDL is the best HDL, it's just a question of tweaking it.
Example:
when-else in architecture declarative section
(inline structure it's often harder to read because lines become long and
they must be cut)
architecture .... of .... is
constant C_ABC : integer := G_WIDTH when G_XYZ else
G_WIDTH+1 when G_MNO else
G_WIDTH-1;
could be also written with
if then-elsif then-else-end if in architecture declarative section
(it's often easier to read someting without an inline structure because
lines are shorter)
architecture .... of .... is
if G_XYZ then
constant C_ABC : integer := G_WIDTH;
elsif G_MNO then
constant C_ABC : integer := G_WIDTH+1;
else
constant C_ABC : integer := G_WIDTH-1;
end if;
if then-elsif then-else-end if in architecture concurrent section
(equivalent to if generate)
if G_XYZ then
u1: entity work.abc
generic map(
)
port map (
);
else
u2: entity work.def
generic map(
)
port map (
);
end if;
I see that some people work on a wilcard for the sensitivity list. Please
don't add a new keyword ('all' like the proposition), use the known wildcard
'*' like in unix, dos/windows, verilog, ...
process (*)
process (all) could be non backward compatible (you have more chance to be
hit by a ligthning but just in case).
with you proposition in vhdl200x, this process will have a different
behaviour in simulation.
process (all) -- vhdl 93 (simulation only, not for synthesis)
begin
if all then
abc <= xyz;
else
abc <= def;
end if;
end process;
What do you (Jim, Ben, anybody) think about these?
regards
fe