Asynch. signal

Discussion in 'VHDL' started by john, Jan 6, 2006.

  1. john

    john Guest

    Hello,

    I have interfaced a 8 bit parallel data bus and a clock signal of the
    USB device to a CPLD. I need to store 32bits of data in a buffer. And
    then serially shift out the 32 bits. The loading of the data into the
    buffer can only be done by using the clock coming from the USB device
    because when USB generates data it generates clock with it. So I
    decided to use another clock to serial out the data. The problem is the
    handshaking between the USB process and the serial out process. The two
    processes have different clocks so the serial out process could miss
    the signal form the USB process that the buffer is ready to be serial
    out.
    Please advice a solution, thanks

    John
    john, Jan 6, 2006
    #1
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