asynchronous counter an Xilinx FPGA for a newbie

[Georges Konstantinidis]

Dear all
I'm deseprately trying to make an asynchronous counter to count the number
of inputs I have on a pin. I also want a reset input.
I copied the last version of my code at this e-mail .
The synthesis looks good but an error comes at the implementation design. I
don't kow to to do any more.
Thank you for fixing my bugs, Georges.


library ieee;
use ieee.std_logic_1164.all;

entity counter is
port(Load, Rst: in std_logic;
LED: out std_logic_vector(0 to 7)
);
end counter;

architecture behaviour of counter is
signal Qreg: std_logic_vector(0 to 7);

begin
process(Rst, Load)
begin
if Rst = '1' then -- Async reset
Qreg <= "00000000";
elsif Load='1' then
Qreg<=Qreg+1;
end if;

end process;

LED <= Qreg;

end behaviour;

 

[Egbert Molenkamp]

Your synthesis tool does not synthesize:

process(Rst, Load)
begin
if Rst = '1' then -- Async reset
Qreg <= "00000000";
elsif Load='1' then
Qreg<=Qreg+1;
end if;

But it synthesizes it with a different sensitivity list:
process(Rst, Load, QREG)

If you simulate (before synthesis) the process with this sensitive list
you will notice the loop if LOAD='1' and rst='0'.

I'm not sure if you want a latch, but a flipflop solves the problem.
Replace

elsif Load='1' then

with
elsif rising_edge(Load) then

Egbert Molenkamp

 

[Andy Peters]

Dear all
I'm deseprately trying to make an asynchronous counter to count the number
of inputs I have on a pin. I also want a reset input.
I copied the last version of my code at this e-mail .
The synthesis looks good but an error comes at the implementation design. I
don't kow to to do any more.
Thank you for fixing my bugs, Georges.


library ieee;
use ieee.std_logic_1164.all;

entity counter is
port(Load, Rst: in std_logic;
LED: out std_logic_vector(0 to 7)
);
end counter;

architecture behaviour of counter is
signal Qreg: std_logic_vector(0 to 7);

begin
process(Rst, Load)
begin
if Rst = '1' then -- Async reset
Qreg <= "00000000";
elsif Load='1' then
Qreg<=Qreg+1;
end if;

end process;

LED <= Qreg;

end behaviour;

Why do you want to do an async counter? No clock available?

What is the implementation error? (Actually, I know what it is -- but
I want to know what you think it is.)

Think about:

What happens if neither Rst nor Load are asserted?

--a

 

[Georges Konstantinidis]

What do you mean by saying "asserted"?

"Georges Konstantinidis" <[email protected]> wrote in

Why do you want to do an async counter? No clock available?

What is the implementation error? (Actually, I know what it is -- but
I want to know what you think it is.)

Think about:

What happens if neither Rst nor Load are asserted?

--a

 

[Andrew Greensted]

Try this:

library ieee;
use ieee.std_logic_1164.all;

entity counter is
port( Load: in std_logic;
Rst: in std_logic;
LED: out std_logic_vector(0 to 7));

end counter;

architecture behaviour of counter is
begin

cnt : process(Rst, Load)

variable count : std_logic_vector(7 downto 0);

begin

if (Rst = '1' then) then
count := "00000000";
else if (Load'event and Load='1') then
count := count + 1;
end if;

LED <= count;

end process cnt;

end behaviour;

Now make sure that Load is 'locked' to a clock input on the FPGA, or
you'll probably get complaints of a logic line driving clock inputs.
Try using something like:

attribute LOC : string;
attribute LOC of signal Load : signal is "pin number";

Every time that a rising edge of Lock occurs, the variable count is
incremented. LED will be loaded with the value of count each time the
process 'runs' (I assume this is what you want?).

 

[Andy Peters]

What do you mean by saying "asserted"?

"Asserted" means "put into the active state."

It's a very common term. It's useful because it nicely ignores the
detail of whether the signal is active low or active high.

--a

 

[Georges Konstantinidis]

Thanks for the info.

"Georges Konstantinidis" <[email protected]> wrote in

 

[Georges Konstantinidis]

Hello Andrew,
I was endeed using a "normal I/O port" which is synchronous or asynchronous
according to the datasheets. I should be able to use it.
Or I miss something.
I found also a template in ISE called "debounce circuit" which seems to
work.
In any case I will also try what you said
Thanks everyone for you cooperation, Georges.

 

[Sajan]

First of all , when you say that you are implementing a counter,
what are you going to count???????

assuming whatever you are going to count is A, then
use this code to increment the count
if A'event and A = '1' -- or A = '0' whatever be the case
count := count + 1;
end if;

or else you might endup counting something else or endup in a
infinite loop as u see to be now.

 

[Georges Konstantinidis]

I want to count pulses coming from outside the FPGA (Spartan IIe on the
Burched board) and displays the valus on a 7 digits segment.
I tried already your code. the synthesis works, but not the implementation
design. I created an UCF file to assign the pin, maybe this file creates
problem.
I do not know at which moment of the process I should assign the pins.
Georges.

 

[Andrew Greensted]

I think this boils down to what is considered good design practice.
If you want to count the edges of a single input line, then it really
should be considered as a clock input, and therefore you should be using
a dedicated clock input pin.

If you use a standard IO pin, then ISE will grumble about using it to
drive clock inputs. If you're stuck with this setup, then you really
should be sampling this IO line. If you're expecting a fairly low input
frequency, and a long mark and space time (high and low time) then this
should be easy enough.

In a nutshell. If you where going to do this in good old fashioned 74
series, you'd plug the signal you want to count into the counter clock
input. For similar reasons you should connect the same signal into the
FPGA clock input.

Andy

P.S. Chances are someone else knows better. I'm quite willing to be
proved wrong!!

 

[glen herrmannsfeldt]

Dear all
I'm deseprately trying to make an asynchronous counter to count the number
of inputs I have on a pin. I also want a reset input.
I copied the last version of my code at this e-mail .
The synthesis looks good but an error comes at the implementation design. I
don't kow to to do any more.
Thank you for fixing my bugs, Georges.

(snip of VHDL code)

If you write it in Verilog I might be able to tell you.

I don't think it looks like an asynchronous (ripple) counter,
though. It might be that you can't make ripple counters
on the system your synthesis is targeting.

-- glen

 

[ckyz]

May i ask a quetion here....

what is the difference between asynchronous and synchrounous counter???