asynchronous design basic

Discussion in 'VHDL' started by airol, Oct 14, 2007.

  1. airol

    airol Guest

    Hi guys,

    I'm a beginner and would like to learn asynchronous design.

    1) anyone can explain what is this mean:

    "Asynchronous designs offer an interesting alternative by keeping the
    assumption that signals are binary but removing the assumption that
    time is discrete"

    2) i've google for asynchronous design tutorial but could'nt found
    anything useful. does anyone know links or documents on asynchronous
    design for beginners?

    thanks in advance.

    regards
    hairo,
    Liverpool JMU
     
    airol, Oct 14, 2007
    #1
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  2. On Sun, 14 Oct 2007 02:11:06 -0700, airol <> wrote:

    >I'm a beginner and would like to learn asynchronous design.


    Looks like you're about 35 miles too far west :)
    A brief trip along the cyber-M62 will get you to

    http://intranet.cs.man.ac.uk/apt/projects/processors/amulet/

    which should start you off on various lines of enquiry.
    Don't start arguing about football, though.

    Also, try googling for "Muller C-element", and also
    look at Handshake Solutions products.

    Sometimes, asynch design is known as "self timed logic".
    That may help.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Oct 14, 2007
    #2
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  3. Jonathan Bromley <> writes:
    > Looks like you're about 35 miles too far west :)
    > A brief trip along the cyber-M62 will get you to
    >
    > http://intranet.cs.man.ac.uk/apt/projects/processors/amulet/


    Just to add to that there is also the ARM996HS, a fully 5TE ISA
    compatible embedded core

    http://www.arm.com/products/CPUs/ARM996HS.html

    Regards
    Marcus

    --
    note that "property" can also be used as syntaxtic sugar to reference
    a property, breaking the clean design of verilog; [...]

    (seen on http://www.veripool.com/verilog-mode_news.html)
     
    Marcus Harnisch, Oct 16, 2007
    #3
  4. airol

    airol Guest

    On Oct 16, 12:25 pm, Marcus Harnisch <> wrote:
    > Jonathan Bromley <> writes:
    > > Looks like you're about 35 miles too far west :)
    > > A brief trip along the cyber-M62 will get you to

    >
    > >http://intranet.cs.man.ac.uk/apt/projects/processors/amulet/

    >
    > Just to add to that there is also the ARM996HS, a fully 5TE ISA
    > compatible embedded core
    >
    > http://www.arm.com/products/CPUs/ARM996HS.html
    >
    > Regards
    > Marcus
    >
    > --
    > note that "property" can also be used as syntaxtic sugar to reference
    > a property, breaking the clean design of verilog; [...]
    >
    > (seen onhttp://www.veripool.com/verilog-mode_news.html)


    thanks jonathan and marcus...
    seem that i need to read a lot of stuff..

    regards,
    hairo
     
    airol, Oct 17, 2007
    #4
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