automating bringing of signals in hierarchical VHDL model to toplevel entity

Discussion in 'VHDL' started by fearg, Jul 20, 2011.

  1. fearg

    fearg Guest

    Hi, I’d be grateful if anyone could advise on whether an application
    is available to do the following for VHDL models.
    Fearghal

    1. Make a replica copy of a selected multi-file and hierarchical VHDL
    design
    2. Modify each VHDL file in the copied hierarchical VHDL model
    (possibly using the make file sequence), in order to bring all (or
    selected) signals to the top level VHDL entity.
    3. Steps:
    a. modify each VHDL files in turn to bring every (or selected)
    internal signal as an output signals in VHDL entity
    b. Modify the associated component declarations within package files
    to reflect the modified entity ports
    c. Rebuild the VHDL hierarchy adding the new output ports to all
    entities in the hierarchy
    d. Modify all port map assignments to mirror the extended entity
    ports.

    My application requires interpreting any existing VHDL model,
    selecting signals from within the VHDL model to bring to the top level
    entity in order to connect to a series of display devices. I do not
    wish to modify the underlying VHDL code.
     
    fearg, Jul 20, 2011
    #1
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  2. On Jul 20, 3:09 pm, fearg <> wrote:
    > Hi, I’d be grateful if anyone could advise on whether an application
    > is available to do the following for VHDL models.
    > Fearghal
    >
    > 1.      Make a replica copy of a selected multi-file and hierarchical VHDL
    > design
    > 2.      Modify each VHDL file in the copied hierarchical VHDL model
    > (possibly using the make file sequence), in order to bring all (or
    > selected) signals to the top level VHDL entity.
    > 3.      Steps:
    > a.      modify each VHDL files in turn to bring every (or selected)
    > internal signal as an output signals in VHDL entity
    > b.      Modify the associated component declarations within packagefiles
    > to reflect the modified entity ports
    > c.      Rebuild the VHDL hierarchy adding the new output ports to all
    > entities in the hierarchy
    > d.      Modify all port map assignments to mirror the extended entity
    > ports.
    >
    > My application requires interpreting any existing VHDL model,
    > selecting signals from within the VHDL model to bring to the top level
    > entity in order to connect to a series of display devices. I do not
    > wish to modify the underlying VHDL code.


    It seems VHDL-2008 has some support similar to this. Doulos says that
    it is not synthesizable, however.
    http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/#hierarchicalnames
    Look at the section Hierarchical Names.
     
    Colin Beighley, Jul 21, 2011
    #2
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  3. fearg

    KJ Guest

    On Jul 20, 6:09 pm, fearg <> wrote:
    >
    > My application requires interpreting any existing VHDL model,
    > selecting signals from within the VHDL model to bring to the top level
    > entity in order to connect to a series of display devices. I do not
    > wish to modify the underlying VHDL code.


    The easiest method to do what you say in the above paragraph is to
    simply use the debug capabilities of the synthesis tool. Each tool
    will let you select arbitrary signals from within a design and bring
    them out to a set of pins which you select. These signals are
    generally intended to be connected to a logic analyzer...but there is
    no reason they can't be connected to the display devices that you
    require. No code changes required.

    However, if you have some other reason for requiring a VHDL model thus
    leading to your steps 1-3d than this method won't work. So you need
    to decide if you're looking for a VHDL model or simply something that
    is implemented in hardware. If it's hardware only, use the logic
    analyzer interface approach.

    Kevin Jennings
     
    KJ, Jul 21, 2011
    #3
  4. fearg

    fearg Guest

    thanks for the suggestions Colin and Kevin.
    I'll look into the synthesis debug and VHDL-2008 options.
    However, Ideally I'd like an easy to use an application independent of
    synthesis tools
    and may have to develop a generic solution myself.

    Fearghal Morgan
     
    fearg, Jul 21, 2011
    #4
  5. Re: automating bringing of signals in hierarchical VHDL model totop level entity

    On 7/20/2011 11:56 PM, fearg wrote:
    > thanks for the suggestions Colin and Kevin.
    > I'll look into the synthesis debug and VHDL-2008 options.
    > However, Ideally I'd like an easy to use an application independent of
    > synthesis tools


    How will you connect the "display devices" to the fpga
    without editing code and running synthesis to make the new interface.

    > and may have to develop a generic solution myself.


    1. Copy code
    2. Edit the code (manual or script)
    3. Synthesize the code and load an fpga image
    4. Hook up the displays and test.

    Seems to me that it might be easier
    to write a testbench and watch the internal waves directly,
    as Kevin suggests.

    -- Mike Treseler
     
    Mike Treseler, Jul 21, 2011
    #5
  6. fearg

    fearg Guest

    Colin,

    the hierarchical access in VHDL-2008 is useful. I do need to
    synthesise the model with signal brought to the top level though.
    Fearghal
    >
    > It seems VHDL-2008 has some support similar to this. Doulos says that
    > it is not synthesizable, however.http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200...
    > Look at the section Hierarchical Names.
     
    fearg, Jul 22, 2011
    #6
  7. fearg

    fearg Guest

    Kevin,

    I generally use Xilinx XST synthesis tool. Could you please point me
    to the debug facility within XST which allows the bringing of internal
    signals to the top level (if this exists)?

    I should clarify my requirement further:
    For any existing design VHDL model entity (e.g, designX), I wish to
    automatically modify the VHDL files to bring selected output signals
    from low levels of the design hierarchy to the designX entity. I then
    instantiate designX within another VHDL model (designTop) which
    contains the host interface and display device controller, and connect
    the newly accessible signals as required for output to host and
    display devices.
    If the above can be automated, I can quickly take any design and
    connect its internal signals to my host and display interfaces.
    I do not wish to use a logic analyser facility.


    > The easiest method to do what you say in the above paragraph is to
    > simply use the debug capabilities of the synthesis tool.  Each tool
    > will let you select arbitrary signals from within a design and bring
    > them out to a set of pins which you select.  These signals are
    > generally intended to be connected to a logic analyzer...but there is
    > no reason they can't be connected to the display devices that you
    > require.  No code changes required.
    >
    > However, if you have some other reason for requiring a VHDL model thus
    > leading to your steps 1-3d than this method won't work.  So you need
    > to decide if you're looking for a VHDL model or simply something that
    > is implemented in hardware.  If it's hardware only, use the logic
    > analyzer interface approach.
    >
    > Kevin Jennings
     
    fearg, Jul 22, 2011
    #7
  8. fearg

    fearg Guest

    Hi,

    if I can extracta listing of component and signal hierarchy from ISE
    (to a file), I could investigate writing a program to automate the
    addition and connection of lower level signals up to the top level.
    Its tedious manually, and would benefit from automation.

    I'd require the generation of a listing something like the following
    from an EDA tool:

    topLevel/LA1:A1/LB1:B1/LC1:C1/sigX sigLC1X
    where:
    LA1 is the label for component A1, instantiated in topLevel VHDL
    model
    LB1 is the label for component B1, instantiated in A1 VHDL model
    LC1 is the label for component C1, instantiated in B1 VHDL model
    sigX is VHDL model C1 entity signal
    sigLC1X is the port map signal in the VHDL model B1, used to connect
    to component C1 port sigX


    topLevel/LA1:A1/LB1:B1/LC1:C1/sigY sigLC1Y
    topLevel/LA1:A1/LB1:B1/LC2:C1/sigX sigLC2X
    topLevel/LA1:A1/LB1:B1/LC2:C1/sigY sigLC2Y
    topLevel/LA1:A1/LB1:B1/LC3:C2/sigP sigLC3P
    etc


    Note: in this example, component C1 is used twice in VHDL model B1.
    sigLC2X is the port map signal in the VHDL model B1, used to
    connect to component C2 port sigX

    I would be grateful for any advice.

    regards,

    Fearghal
     
    fearg, Jul 24, 2011
    #8
  9. Re: automating bringing of signals in hierarchical VHDL model totop level entity

    On 7/24/2011 3:53 PM, fearg wrote:
    > Hi,
    >
    > if I can extracta listing of component and signal hierarchy from ISE
    > (to a file),


    Emacs speedbar does it for you, you only need the vhdl file(s).

    > I could investigate writing a program to automate the
    > addition and connection of lower level signals up to the top level.
    > Its tedious manually, and would benefit from automation.
    >


    For testing purposes you may add a jtag port to every component, connect
    it in a daisy chain and play around with Boundary Scan Register and
    Instruction Register. But you cannot have it operational while you are
    in (IN/EX)TEST mode.

    > I'd require the generation of a listing something like the following
    > from an EDA tool:

    [snip]

    > Note: in this example, component C1 is used twice in VHDL model B1.
    > sigLC2X is the port map signal in the VHDL model B1, used to
    > connect to component C2 port sigX
    >


    I once was convinced that defining the signals in a package so that they
    are seen as global and therefore "available" to the whole hierarchy was
    a good thing. In that case I could have set the registers in one module
    and use it in another without the need to go through In/Out.
    In that approach connecting a signal to the top level was as simple as
    doing:

    pin_out <= global_signal;

    I found later on it was a very bad practice, since it resulted in a very
    poorly reusable code and I spent most of my time trying to remember
    where the heck in my code I was using those registers (pretty much the
    same as any other programming/description language).

    > My application requires interpreting any existing VHDL model,
    > selecting signals from within the VHDL model to bring to the top level
    > entity in order to connect to a series of display devices. I do not
    > wish to modify the underlying VHDL code.


    I'm assuming your "existing VHDL model" is an open hierarchical model
    where you have access to all the components interfaces it uses. If that
    is the case editing the code and picking up the signals you want (as
    suggested) is much simpler.

    If your "existing VHDL model" is the output of an edif2vhdl converter or
    a back-annotate process there's no way to do what you want, since I'm
    pretty convinced the output vhdl would be rather "flat" as opposed to
    hierarchical.

    Bear in mind that if a signal is not accessible from the top level it
    might be a good thing. After all you are interested in the functionality
    of the code, not the details of the flops and gates.
    And if you are debugging the module there's no better place than your
    simulation, much more effective and less time consuming. Set aside that
    if your are targeting a antifuse logic device all your tries will end up
    in a lot of chips thrown out of the window.

    Al
     
    Alessandro Basili, Jul 26, 2011
    #9
  10. fearg

    fearg Guest

    Al,

    thankyou for the suggestions. Please excuse the delay in replying.
    I've been on vacation.
    I will try the emacs solution.
    Also, since I plan to replicate the original design and modify the
    copy as described, the global signal suggestion may be be useful.

    regards,

    Fearghal
     
    fearg, Aug 5, 2011
    #10
  11. On Jul 21, 12:09 am, fearg <> wrote:
    > Hi, I’d be grateful if anyone could advise on whether an application
    > is available to do the following for VHDL models.
    > Fearghal
    >
    > 1.      Make a replica copy of a selected multi-file and hierarchical VHDL
    > design
    > 2.      Modify each VHDL file in the copied hierarchical VHDL model
    > (possibly using the make file sequence), in order to bring all (or
    > selected) signals to the top level VHDL entity.
    > 3.      Steps:
    > a.      modify each VHDL files in turn to bring every (or selected)
    > internal signal as an output signals in VHDL entity
    > b.      Modify the associated component declarations within packagefiles
    > to reflect the modified entity ports
    > c.      Rebuild the VHDL hierarchy adding the new output ports to all
    > entities in the hierarchy
    > d.      Modify all port map assignments to mirror the extended entity
    > ports.
    >
    > My application requires interpreting any existing VHDL model,
    > selecting signals from within the VHDL model to bring to the top level
    > entity in order to connect to a series of display devices. I do not
    > wish to modify the underlying VHDL code.


    Seems like you need a powerful VHDL refactoring tool.

    Sigasi HDT (http://www.sigasi.com/sigasi-hdt) does not completely
    automate the transformation you describe, but it will definitely help
    you avoid errors and will save you a lot of time. With Sigasi you can
    easily add ports and keep your complete design hierarchy consistent.

    If you are a student you can get an educational license, otherwise you
    can download a 4-week trial via http://www.sigasi.com/user/register

    Regards,
    Hendrik.
     
    Hendrik Eeckhaut, Aug 8, 2011
    #11
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