Avoiding gated clocks for counters

Discussion in 'VHDL' started by c64, May 5, 2009.

  1. c64

    c64

    Joined:
    Apr 24, 2009
    Messages:
    11
    Hi,

    After reading some posts on this newsgroup, I have understood that gated clocks is something one would like to avoid in FPGA design. The following code is for a counter:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

    ENTITY counter2rev2 IS
    PORT(
    ENC : IN std_logic;
    CLK2 : IN std_logic;
    COUNT2 : OUT std_logic_vector (18 DOWNTO 0)
    );


    END counter2rev2 ;

    ARCHITECTURE struct OF counter2rev2 IS
    signal count2Int : std_logic_vector(18 downto 0);
    constant allOnes : std_logic_vector(18 downto 0) := (others => '1');
    BEGIN
    counter : process (ENC,CLK2)
    begin
    if ENC = '0' then
    count2Int <= (others => '0');
    elsif rising_edge(CLK2) then
    if (unsigned(count2Int) = unsigned(allOnes)) then
    count2Int <= (others => '0');
    else
    count2Int <= (unsigned(count2Int) + '1');
    end if;
    end if;
    end process;
    COUNT2 <= count2Int;
    END ARCHITECTURE struct;


    If I compile this as a stand-alone code, I get no warnings or errors. However, if I use it as a component in a larger system, I get the warning message that "The clock for counter 'count2Int' is gated", highlighting the line "count2Int <= (unsigned(count2Int) + '1');"

    How should I change the design to avoid this gated clock warning?

    Thanks!
    c64, May 5, 2009
    #1
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  2. c64

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Well the problem can't be found in this code.
    you must look at the path of CLk2, which properly scale down.

    Jeppe
    jeppe, May 6, 2009
    #2
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