avoiding GCLK

Discussion in 'VHDL' started by Mastupristi, Nov 20, 2003.

  1. Mastupristi

    Mastupristi Guest

    I use Xilinx ise web pack 6.1 sp 2.

    In my project I have a signal that is used as clock in only one flip
    flop.
    I have a constrain that place this signal on a generic iob.

    in the map process I obtain the following error:
    Using target part "2s50eft256-6".
    ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol
    "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be
    LOCed to GCLKIOB site.

    How can I force this signal to be placed in a non-GCLK pin?
    There is some vhdl directive?

    thanks


    --
    Mastupristi?

    Posted from X-Privat Free NNTP server - www.x-privat.org
     
    Mastupristi, Nov 20, 2003
    #1
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  2. Mastupristi wrote:

    > In my project I have a signal that is used as clock in only one flip
    > flop.


    > How can I force this signal to be placed in a non-GCLK pin?
    > There is some vhdl directive?


    Consider using a clock enable input rather than
    having two clocks.

    -- Mike Treseler
     
    Mike Treseler, Nov 20, 2003
    #2
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  3. Mastupristi wrote:
    > I use Xilinx ise web pack 6.1 sp 2.
    >
    > In my project I have a signal that is used as clock in only one flip
    > flop.
    > I have a constrain that place this signal on a generic iob.
    >
    > in the map process I obtain the following error:
    > Using target part "2s50eft256-6".
    > ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol
    > "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be
    > LOCed to GCLKIOB site.
    >
    > How can I force this signal to be placed in a non-GCLK pin?
    > There is some vhdl directive?
    >
    > thanks


    Since you have only 1 flip flop to be clocked, you don't need a global
    clock net. (The global clock net is to allow you to clock many flip
    flops simultaneously with little skew.) So don't use the IBUFG, use a
    simple IBUF (or nothing at all if this is a pure VHDL design). You will
    simply incur the delay from the I/O pad to the clock of the flip flop.
     
    Marc Guardiani, Nov 21, 2003
    #3
  4. Mastupristi

    Duane Clark Guest

    Mastupristi wrote:
    > I use Xilinx ise web pack 6.1 sp 2.
    >
    > In my project I have a signal that is used as clock in only one flip
    > flop.
    > I have a constrain that place this signal on a generic iob.
    >
    > in the map process I obtain the following error:
    > Using target part "2s50eft256-6".
    > ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol
    > "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be
    > LOCed to GCLKIOB site.
    >
    > How can I force this signal to be placed in a non-GCLK pin?
    > There is some vhdl directive?
    >


    Did you try:
    attribute clock_buffer: string;
    attribute clock_buffer of ONEFFCLK: signal is "ibuf";


    --
    My real email is akamail.com@dclark (or something like that).
     
    Duane Clark, Nov 21, 2003
    #4
  5. Marc Guardiani wrote:
    > Since you have only 1 flip flop to be clocked, you don't need a global
    > clock net. (The global clock net is to allow you to clock many flip
    > flops simultaneously with little skew.) So don't use the IBUFG, use a
    > simple IBUF (or nothing at all if this is a pure VHDL design). You will
    > simply incur the delay from the I/O pad to the clock of the flip flop.


    The problem is that XST automatically instantiates an IBUFG component
    for all clock-like signals (also in plain VHDL). To avoid this you can
    instantiate an IBUF explicitly. This will solve the "Illegal LOC
    constraint" error.

    /Rienk
     
    Rienk van der Scheer, Dec 1, 2003
    #5
  6. Does it do this even if you turn off "automatically add I/O buffers" (or
    words to that effect)?

    Rienk van der Scheer wrote:

    > Marc Guardiani wrote:
    >
    >> Since you have only 1 flip flop to be clocked, you don't need a global
    >> clock net. (The global clock net is to allow you to clock many flip
    >> flops simultaneously with little skew.) So don't use the IBUFG, use a
    >> simple IBUF (or nothing at all if this is a pure VHDL design). You
    >> will simply incur the delay from the I/O pad to the clock of the flip
    >> flop.

    >
    >
    > The problem is that XST automatically instantiates an IBUFG component
    > for all clock-like signals (also in plain VHDL). To avoid this you can
    > instantiate an IBUF explicitly. This will solve the "Illegal LOC
    > constraint" error.
    >
    > /Rienk
    >
    >
     
    Marc Guardiani, Dec 3, 2003
    #6
  7. Marc Guardiani wrote:
    > Does it do this even if you turn off "automatically add I/O buffers" (or
    > words to that effect)?


    I wasn't aware of that option, but when you read the online help, you
    know no I/O buffers are added when this option is off. In that case you
    have to add all I/O buffers manually in your VHDL design.

    /Rienk

    > Rienk van der Scheer wrote:
    >
    >> Marc Guardiani wrote:
    >>
    >>> Since you have only 1 flip flop to be clocked, you don't need a
    >>> global clock net. (The global clock net is to allow you to clock many
    >>> flip flops simultaneously with little skew.) So don't use the IBUFG,
    >>> use a simple IBUF (or nothing at all if this is a pure VHDL design).
    >>> You will simply incur the delay from the I/O pad to the clock of the
    >>> flip flop.

    >>
    >>
    >>
    >> The problem is that XST automatically instantiates an IBUFG component
    >> for all clock-like signals (also in plain VHDL). To avoid this you can
    >> instantiate an IBUF explicitly. This will solve the "Illegal LOC
    >> constraint" error.
    >>
    >> /Rienk
    >>
    >>

    >
     
    Rienk van der Scheer, Dec 4, 2003
    #7
  8. Mastupristi

    sharat babu Guest

    Hi...

    First of all check wether u have constrained any signals with respect
    this generic clocks..if yes that is the root cause of the
    problem..else if no then u just assign the buffer as ibuf instead of
    ibufg...this should solve the problem..

    sharat


    Mastupristi <cialdi_NO_SP@AM_firenze.net> wrote in message news:<20031120133855.00002ff3.cialdi_NO_SP@AM_firenze.net>...
    > I use Xilinx ise web pack 6.1 sp 2.
    >
    > In my project I have a signal that is used as clock in only one flip
    > flop.
    > I have a constrain that place this signal on a generic iob.
    >
    > in the map process I obtain the following error:
    > Using target part "2s50eft256-6".
    > ERROR:MapLib:93 - Illegal LOC on IPAD symbol "din<0>" or BUFGP symbol
    > "din_0_BUFGP" (output signal=din_0_BUFGP), IPAD-IBUFG should only be
    > LOCed to GCLKIOB site.
    >
    > How can I force this signal to be placed in a non-GCLK pin?
    > There is some vhdl directive?
    >
    > thanks
     
    sharat babu, Dec 10, 2003
    #8
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