ayuda / help

Discussion in 'VHDL' started by xecron, Oct 4, 2007.

  1. xecron

    xecron Guest

    how to generic map (a1)


    ejem.
    entity test is

    end test;



    architecture cuerpo_test of test is

    signal AA integer; -- NO CONSTANT

    begin

    ....

    ....



    llamada: entity work.red (estructural) generic map ( AA ) port map(
    ......)

    end cuerpo test;



    entity red

    generic (AA :integer);

    port (.......);

    end red
    xecron, Oct 4, 2007
    #1
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