back-annotation SDF Timing Simulation

[Chao]

Hello, there.

I got the following error message when I tried to do the
back-annotation SDF Timing Simulation within ModelSim 5.7g.

1st trial: load & simulate the top testbench entity, meanwhile apply
the sdf file.
commands: vsim –sdfmax
/=D:/!Master_Project/VHDL/Src/s3lc_verif_timesim.sdf -t ps
work.s3lc_verif_tb

Then I got the msg as follows:
# ** Error: (vsim-SDF-3250) D:/VHDL/Src/s3lc_verif_timesim.sdf(12):
Failed to find INSTANCE '/s3lc_verif_tb/DISPLAY_OPV_6_228_SW0_G'.
# ** Warning: (vsim-SDF-3442) D:/VHDL/Src/s3lc_verif_timesim.sdf: Try
instance '/s3lc_verif_tb/s3lc_verif_inst'. It contains all instance
paths from this file.

2nd trial: after that, I add the '/s3lc_verif_tb/s3lc_verif_inst' to
the region.
commands: vsim –sdftyp
/S3LC_VERIF_TB/S3LC_VERIF_INST/=D:/!Master_Project/VHDL/Src/s3lc_verif_timesim.sdf
-t ps work.s3lc_verif_tb

Then I got large amounts of errors which look like
# ** Error: (vsim-SDF-3240) D:/VHDL/Src/s3lc_verif_timesim.sdf(8219):
Instance '/s3lc_verif_tb/s3lc_verif_inst/static_disp_lcd_inst_state_0'
does not have a generic named 'tperiod_clk_posedge'.

3rd trial: finally, I have to ignore and disable all warnings and
errors by using command: vsim -sdftyp
/s3lc_verif_tb/s3lc_verif_inst=D:/VHDL/Src/s3lc_verif_timesim.sdf
-sdfnoerror -sdfnowarn -t ps work.s3lc_verif_tb

then I got no errors and could continue.

but I think this solution is not correct, do you agree with me?

thank you for your answer.

Chao.

 

[Tim Hubberstey]

Hello, there.

I got the following error message when I tried to do the
back-annotation SDF Timing Simulation within ModelSim 5.7g.

1st trial: load & simulate the top testbench entity, meanwhile apply
the sdf file.
commands: vsim –sdfmax
/=D:/!Master_Project/VHDL/Src/s3lc_verif_timesim.sdf -t ps
work.s3lc_verif_tb

Then I got the msg as follows:
# ** Error: (vsim-SDF-3250) D:/VHDL/Src/s3lc_verif_timesim.sdf(12):
Failed to find INSTANCE '/s3lc_verif_tb/DISPLAY_OPV_6_228_SW0_G'.
# ** Warning: (vsim-SDF-3442) D:/VHDL/Src/s3lc_verif_timesim.sdf: Try
instance '/s3lc_verif_tb/s3lc_verif_inst'. It contains all instance
paths from this file.

2nd trial: after that, I add the '/s3lc_verif_tb/s3lc_verif_inst' to
the region.
commands: vsim –sdftyp
/S3LC_VERIF_TB/S3LC_VERIF_INST/=D:/!Master_Project/VHDL/Src/s3lc_verif_timesim.sdf
-t ps work.s3lc_verif_tb

Then I got large amounts of errors which look like
# ** Error: (vsim-SDF-3240) D:/VHDL/Src/s3lc_verif_timesim.sdf(8219):
Instance '/s3lc_verif_tb/s3lc_verif_inst/static_disp_lcd_inst_state_0'
does not have a generic named 'tperiod_clk_posedge'.

3rd trial: finally, I have to ignore and disable all warnings and
errors by using command: vsim -sdftyp
/s3lc_verif_tb/s3lc_verif_inst=D:/VHDL/Src/s3lc_verif_timesim.sdf
-sdfnoerror -sdfnowarn -t ps work.s3lc_verif_tb

then I got no errors and could continue.

but I think this solution is not correct, do you agree with me?

You're right that you're wrong.

It sounds like you're trying to simulate your synthesis source RTL code
with the SDF file. This will never work, unless your source is 100%
structural.

What you need to do is apply the SDF to the synthesized output netlist.
Depending on your tools, you will probably need to issue some kind of
command to have this netlist created. It will consist totally of
instantiations of gate-level primitives.

If my assumption is wrong and you *are* using the gate-level netlist,
then it could be that your modelsim.ini is pointing to the wrong library.

In any case, the problem is that the VHDL does not contain the correct
primitives for the SDF file you are using. Check the manuals for your
synthesis tools.