bad synchronous description error

Discussion in 'VHDL' started by fpgawizz, Mar 3, 2005.

  1. fpgawizz

    fpgawizz Guest

    I am trying to synthesize this piece of code
    entity Coin is
    Port ( reset : in std_logic;
    quarter : in std_logic;
    dime : in std_logic;
    nickel : in std_logic;
    isselvalid : in std_logic;
    d2 : out std_logic_vector(3 downto 0);
    d3 : out std_logic_vector(3 downto 0);
    coinval : out integer range 0 to 95);
    end Coin;

    architecture Behavioral of Coin is
    signal temp : integer range 0 to 95;
    begin

    process(reset,quarter,dime,nickel,isselvalid)
    begin
    if reset = '1' then
    d2 <= "0000";
    d3 <= "0000";
    temp <= 0;
    elsif isselvalid = '1' then
    if quarter'event and quarter = '1' then
    temp <= temp + 25;
    elsif dime'event and dime = '1' then
    temp <= temp + 10;
    elsif nickel'event and nickel = '1' then
    temp <= temp + 5;
    else
    temp <= temp;
    end if;
    else
    temp <= temp;
    end if;
    coinval <= temp;

    case temp is

    when 0 =>
    d2 <= "0000";
    d3 <= "0000";
    when 5 =>
    d2 <= "0101";
    d3 <= "0000";
    when 10 =>
    d2 <= "0000";
    d3 <= "0001";
    when 15 =>
    d2 <= "0101";
    d3 <= "0001";
    when 20 =>
    d2 <= "0000";
    d3 <= "0010";
    when 25 =>
    d2 <= "0101";
    d3 <= "0010";
    when 30 =>
    d2 <= "0000";
    d3 <= "0011";
    when 35 =>
    d2 <= "0101";
    d3 <= "0011";
    when 40 =>
    d2 <= "0000";
    d3 <= "0100";
    when 45 =>
    d2 <= "0101";
    d3 <= "0100";
    when 50 =>
    d2 <= "0000";
    d3 <= "0101";
    when 55 =>
    d2 <= "0101";
    d3 <= "0101";
    when 60 =>
    d2 <= "0000";
    d3 <= "0110";
    when 65 =>
    d2 <= "0101";
    d3 <= "0110";
    when 70 =>
    d2 <= "0000";
    d3 <= "0111";
    when 75 =>
    d2 <= "0101";
    d3 <= "0111";
    when 80 =>
    d2 <= "0000";
    d3 <= "1000";
    when 85 =>
    d2 <= "0101";
    d3 <= "1000";
    when 90 =>
    d2 <= "0000";
    d3 <= "1001";
    when 95 =>
    d2 <= "0101";
    d3 <= "1001";
    when others =>
    d2 <= "1111";
    d3 <= "1111";
    end case;

    end process;
    end Behavioral;

    Quarter,dime and Nickel are 3 buttons that when pressed generate pulse. I
    want to add 25,10 or 5 when they are pressed and pass the value on to a
    display using d2 and d3. I have this error where it says temp has bad
    sysnchrounous desription. Any comments on hw i can fix this?

    thanks
     
    fpgawizz, Mar 3, 2005
    #1
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  2. fpgawizz wrote:

    > process(reset,quarter,dime,nickel,isselvalid)
    > begin
    > if reset = '1' then
    > d2 <= "0000";
    > d3 <= "0000";
    > temp <= 0;
    > elsif isselvalid = '1' then
    > if quarter'event and quarter = '1' then


    Don't use 'event inside an if / elsif or case branch.

    > temp <= temp + 25;
    > elsif dime'event and dime = '1' then


    Don't use 'event in an elsif-branch, if you already have used 'event in a preceding if /
    elsif- or case-branch.

    Don't use two times 'event inside one process except you are very sure, that your
    synthesis tool is capable of synthesizing dual-edge flipflops. This is very rare!


    ....
    > case temp is


    Don't do anything after an elsif branch with an 'event.



    Use the FF-template (you may cut some resets / sets):

    process(async_set, async_reset, clock)
    begin
    if (async_reset='1') then
    -- do some reset (asynchronously)
    elsif (set='1') then
    -- do some set (asynchronously)
    elsif rising_edge(clock) then
    if (sync_set='1') then
    -- do some set (synchronously)
    elsif (sync_reset='1') then
    -- do some reset (synchronously)
    else
    -- do something else
    end if;
    end if;
    end process;

    (I have used rising_edge(clock) instead of (clock'event and clock='1') which is almost the
    same except some simulation specific cases.)

    Ralf
     
    Ralf Hildebrandt, Mar 3, 2005
    #2
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  3. I'd say it's a bad idea to use the if <a>'event and <a> = whatever
    unless a is a clock signal. This is probably where your error is
    coming from

    Tony
     
    dutchgoldtony, Mar 3, 2005
    #3
  4. The pulses for quarter, dime and nickel run off some clock, right?
    If so, you need to make a process based on that clock. T

    process(reset,clk, quarter,dime,nickel,isselvalid)
    begin
    if reset = '1' then
    d2 <= "0000";
    d3 <= "0000";
    temp <= 0;
    elsif clk'event and clk = '1' then
    if isselvalid = '1' then
    if quarter = '1' then
    temp <= temp + 25;
    elsif dime = '1' then
    temp <= temp + 10;
    elsif nickel = '1' then
    temp <= temp + 5;
    else
    temp <= temp;
    end if;
    else
    temp <= temp;
    end if;
    end if;

    That's it! Nothing else, nothing more!

    - Paulo Valentim

    "fpgawizz" <> wrote in message news:<>...
    >
    > process(reset,quarter,dime,nickel,isselvalid)
    > begin
    > if reset = '1' then
    > d2 <= "0000";
    > d3 <= "0000";
    > temp <= 0;
    > elsif isselvalid = '1' then
    > if quarter'event and quarter = '1' then
    > temp <= temp + 25;
    > elsif dime'event and dime = '1' then
    > temp <= temp + 10;
    > elsif nickel'event and nickel = '1' then
    > temp <= temp + 5;
    > else
    > temp <= temp;
    > end if;
    > else
    > temp <= temp;
    > end if;
    > coinval <= temp;
     
    Paulo Valentim, Mar 4, 2005
    #4
  5. You're getting that bad synchronous description because your design
    isn't synchronous. I.E. You have no clock signal in your design as
    Paulo has above which is correct
     
    dutchgoldtony, Mar 4, 2005
    #5
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