basic vhdl queries

[sundar]

hi all,

1) how does it matter for a cpld when i declare a constant or signal
2) what is the difference if i mention default value while
declaration /without declaration
3)
difference between below piece of tristate code
output <= a when enable= '1' else ''z';
and using primitive
tri port map
(
a_in <= a,
oe <= enable,
a_out <= output
)

which is better why?
4) output <= a when (expression1)
else b when (expr2)
else....
...
else n when (exprn)

what is the diff if this combo logic is inside a process block

5) whats the diff between
if ( a and b and c and d)
case x
1:
2:
3:
4:
default

and

if (a and b and c and d and x1)
elseif (a and b and c and d and x2)
elseif (a and b and c and d and x3)
elseif (a and b and c and d and x4)
else

note that internal case x is used as x1,x2,x3 and x4 respectively

pls share your thots

rgs,
sundar

 

[Tricky]

hi all,

1) how does it matter for a cpld when i declare a constant or signal
2) what is the difference if i mention default value while
declaration /without declaration
3)
difference between below piece of tristate code
output <= a when enable= '1' else ''z';
and using primitive
tri port map
(
a_in <= a,
oe <= enable,
a_out <= output
)

which is better why?
4) output <= a when (expression1)
    else b when (expr2)
    else....
    ...
    else n when (exprn)

    what is the diff if this combo logic is inside a process block

5) whats the diff between
if ( a and b and c and d)
    case x
    1:
    2:
    3:
    4:
    default

and

if (a and b and c and d and x1)
elseif (a and b and c and d and x2)
elseif (a and b and c and d and x3)
elseif (a and b and c and d and x4)
else

note that internal case x is used as x1,x2,x3 and x4 respectively

pls share your thots

rgs,
sundar

Oh dear, I detect homework.

Its a shame that this homework seems to be about 10+ years out of
date.

 

[KJ]

hi all,

1) how does it matter for a cpld when i declare a constant or signal

cplds get quite upset about declaring constants, they think they rule
the universe and so they try to destroy all constants. fpgas on the
other hand, being a bit more advanced are quite tolerant of
constants...in regards to signals, they both like to signal ahead, but
occasionally signal to the left or right.

2) what is the difference if i mention default value while
declaration /without declaration

If you mention a default value without a declaration then it's a
secret.

3)
difference between below piece of tristate code
output <= a when enable= '1' else ''z';
and using primitive
tri port map
(
a_in <= a,
oe <= enable,
a_out <= output
)

The first piece has a syntax error...you find it.

which is better why?

The second one is better, because it has no syntax errors. I consider
that to be a major plus, others may disagree. There have been several
heated arguments in this forum about the advantages and disadvantages
of correct syntax code, I hope my meer mention of the topic doesn't
ignite yet another flame war. Google for it.

4) output <= a when (expression1)
    else b when (expr2)
    else....
    ...
    else n when (exprn)

    what is the diff if this combo logic is inside a process block

Inside a process block this combo logic won't compile, again a syntax
error (see above comments).

I've also used "..." in the past, but have usually found that I have
to replace it with coherent logic before the design is done. I've
never tried the "...." approach, looks interesting.

5) whats the diff between
if ( a and b and c and d)
    case x
    1:
    2:
    3:
    4:
    default

and

if (a and b and c and d and x1)
elseif (a and b and c and d and x2)
elseif (a and b and c and d and x3)
elseif (a and b and c and d and x4)
else

note that internal case x is used as x1,x2,x3 and x4 respectively

Note also that neither one will pass a basic syntax check.

Note further that mutually exclusive things as expressed in the first
code are not the same as priority encoding as expressed in the second
code. Personally, I like mutually exclusive things that cannnot
overlap, it just bothers me no end when the gravy from my mashed
potatoes encroaches on the veggies destroying the exclusivity that I
tried to set up. In those situations, I'm forced to use a defined
priority and eat the veggies before the gravy encroaches even though
my preference is for the taters.

pls share your thots

I'm all out of thots.

rgs,
sundar

rgs back atcha

KJ

 

[M. Norton]

What is it with all these unreadable abbreviations young folks are using
today, anyway?

I'm puzzled too. Not even sure what rgs was supposed to be. Best I
could come up with was "root green square" which is nonsensical, but
had a pleasant sound to it ;-).

Mark

 

[pankaj.goel]

Hi friends...what a cool stuff on VHDL forum...But don't u think it is too much... u r getting to critical...
anyways enjoy urself...

 

[KJ]

What is it with all these unreadable abbreviations young folks are using
today, anyway?

Maybe sundar just couldn't afford to purchase vowels. In any case, I just
sent the 'rgs' back to him in case he needed them...whatever they
are...maybe they were 'regards'....or 'rugs'.

73's OM,
- Brian

Abbreviations like "OM"?? Hmmmm

KJ