Basics of VHDL. Whats happening here?

[vikramtheone]

I just started to learn VHDL so kindly support me
I'm getting confused between how <= and := symbols actually work? I know that they have a major difference but I cant really make out as I'm from s/w background.

For example in the following code, when do :=, <= statements execute? Please don't stop at saying one is sequential and other is concurrent, that is where I'm not able to understand please explain more with small examples and other possibilities. I really learn fast with examples.

Also can you please explain to me whats happening in this code? I'm really lost.

******** Code****************
architecture twoproc of test is
signal r, rin : std_logic_vector(7 downto 0);
begin

combinational : process(load, count, d, r)
variable tmp : std_logic_vector(7 downto 0);
begin
if load = ’1’ then tmp := d;
elsif count = ’1’ then tmp := r + 1;
else tmp := r; end if;
rin <= tmp;
q <= r;
end process;

sequential : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end;
*******************************

Thank you all so very much!!!

 

[jeppe]

Well you found one the "cornerstones" of VHDL - the difference between signals and variables.

A signal will not get its value before the process ends while the variable gets its value immediate (as in C++, Java, C# etc.)

I you add "r" to the sensitivity list will your code work nicely. The problem is that "r" must be able to
trigger the process in order to pass the value to q.
But I will surgest that you pass rin directly to q in the clk-driven process.

Please search for the free interactive book on VHDL Evita from aldec. Specially chapter 6 will answer your questions.

Your welcome
Jeppe