bob said:
Hi I have installed a 6 digit 7 segment LCD on my protoboard.
I have a signal (pulses) that I want to count and then display.
I want to send the pulses to 6 cascaded BCD counters.
I will send each BCD output to a BCD to 7 segment Decoder and then out
to my LCD
I am using Xilinx webpack but there is no VHDL BCD counters or BCD to
7 segment modules in its library.
Does enyone have a example code or could they point me to a example on
the web?
A 7 segment LED driver could be converted with a phase input to toggle
the outputs for the LCD.
If there is a better way to do the same thing I would be interested.
Thanks
Martin
Hello Martin,
Use a look-up table if you want to create a BCD to 7 segment converter:
signal BCD_IN: std_logic_vector (3 downto 0);
signal SEG_OUT: std_logic_vector (7 downto 0);
BCD_2_7SEGM:
process(BCD_IN)
begin
case BCD_IN is
when X"0" => SEG_OUT<= "0111111";
when X"1" => SEG_OUT<= "0000110";
when X"2" => SEG_OUT<= "1011011";
when X"3" => SEG_OUT<= "1001111";
when X"4" => SEG_OUT<= "1100110";
when X"5" => SEG_OUT<= "1101101";
when X"6" => SEG_OUT<= "1111101";
when X"7" => SEG_OUT<= "0000111";
when X"8" => SEG_OUT<= "1111111";
when X"9" => SEG_OUT<= "1101111";
when others => SEG_OUT<= "0000000";
end case;
end process;
A BCD counter is probably easiest (quick and dirty) with the following code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity bcdtest is
port (
CLK : in std_logic;
COUNT_OUT : out std_logic_vector (23 downto 0));
end bcdtest;
architecture arch of bcdtest is
signal bcd_count : unsigned (23 downto 0);
begin
COUNTER:
process (CLK)
begin
if CLK'event and CLK = '1' then
if bcd_count (3 downto 0) = "1001" then
bcd_count (3 downto 0) <= (others => '0');
if bcd_count (7 downto 4) = "1001" then
bcd_count (7 downto 4) <= (others => '0');
if bcd_count (11 downto 8) = "1001" then
bcd_count (11 downto 8) <= (others => '0');
if bcd_count (15 downto 12) = "1001" then
bcd_count (15 downto 12) <= (others => '0');
if bcd_count (19 downto 16) = "1001" then
bcd_count (19 downto 16) <= (others => '0');
if bcd_count (23 downto 20) = "1001" then
bcd_count (23 downto 20) <= (others => '0');
else
bcd_count (23 downto 20) <= bcd_count (23 downto 20) + 1;
end if;
else
bcd_count (19 downto 16) <= bcd_count (19 downto 16) + 1;
end if;
else
bcd_count (15 downto 12) <= bcd_count (15 downto 12) + 1;
end if;
else
bcd_count (11 downto 8) <= bcd_count (11 downto 8) + 1;
end if;
else
bcd_count (7 downto 4) <= bcd_count (7 downto 4) + 1;
end if;
else
bcd_count (3 downto 0) <= bcd_count (3 downto 0) + 1;
end if;
end if;
end process;
COUNT_OUT <= std_logic_vector(bcd_count);
end arch;
This code will probably produce a lot of logic. there is probably a cleaner
way to generate a BCD counter, specially with more digits.
This code will create 6 adders and 24 registers (35 slices in Xilinx spartan
2E). There should be a way to use only one adder, because only one of the
digits will count, but I can't come up with that at the moment.
I hope this helps,
Mark.