Hey everyone, I am having trouble writing a behavioral model for a two out of five bit detector. Y is always undefined when I simulate it, what am I doing wrong? Here is the code:
Code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity two_five is -- Begin entity
port(
A, B, C, D, E: in std_logic;
Y: out std_logic
);
end entity two_five; -- End entity
-------------------------------------------------
architecture beh of two_five is -- Begin architecture
signal sig: std_logic_vector (4 DOWNTO 0);
signal cnt: std_logic_vector (1 downto 0) := "00";
begin
sig <= A&B&C&D&E;
process (sig)
begin
for i in 0 to 4 loop
if sig(i) = '1' then
cnt <= cnt + 1;
end if;
if cnt = "10" then--count = 2 then
Y <= '1';
else Y <= '0';
end if;
end loop;
end process;
end beh;