Bi directional data signal in cpu

Discussion in 'VHDL' started by umerarain, May 18, 2006.

  1. umerarain

    umerarain

    Joined:
    May 16, 2006
    Messages:
    5
    i have written one simple alu accumaltor structure and that u can see in following code.my problem is that when i try to simulate i am getting bus conflict,means when i want to put data back to data bus as iam using data bus inout ,it is showing undefined signal 'X' (bus conflict) .can any one help me out in this problem.iam using xiling for vhdl code and simulating it modelsim.




    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    package MP_PACK is

    -- Typdeklarationen:

    type OPTYPE is (NOP,LDAUNM,ADD,SUB);--OPCODE
    end MP_PACK;

    top level

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use WORK.MP_PACK.ALL;

    entity ALU_AKKU is

    generic(DELAY : time := 10 ns);

    port ( CLK ,RESET : in bit;
    DATABUS : inout std_logic_vector(3 downto 0);
    OPCODE : in OPTYPE;
    LOADDABUS : in bit;
    LOADACBUS : in bit
    );

    end ALU_AKKU;

    architecture Behavioral of ALU_AKKU is

    signal ACBUS,ALUOUT : std_ulogic_vector(3 downto 0);

    component ALU_ENT

    generic(DELAY : time:= 10 ns);
    port( DATABUS : in std_ulogic_vector(3 downto 0):= (others=>'0');
    ACBUS : in std_ulogic_vector(3 downto 0):= (others=>'0');
    OPCODE : in OPTYPE;
    ALUOUT : out std_ulogic_vector(3 downto 0):= (others=>'0'));

    end component ALU_ENT;

    component AKKU_ENT

    generic(DELAY : time := 10 ns);
    port( CLK : in bit;
    RESET : in bit;
    ALUOUT : in std_ulogic_vector(3 downto 0):= (others=>'0');
    DATABUS : out std_logic_vector(3 downto 0):= (others=>'0');
    ACBUS : out std_ulogic_vector(3 downto 0):= (others=>'0');
    LOADDABUS : in bit:='0';
    LOADACBUS : in bit:='0'
    );

    end component AKKU_ENT;


    begin

    COMP_1 : ALU_ENT

    generic map (10 ms)
    port map(to_stdulogicvector(DATABUS),ACBUS,OPCODE,ALUOU T);

    COMP_2 : AKKU_ENT

    generic map (10 ms)
    port map(CLK,RESET,ALUOUT,DATABUS,ACBUS,LOADDABUS,LOADA CBUS);



    end Behavioral;

    ALU
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use WORK.MP_PACK.ALL;



    entity ALU_ENT is

    generic(DELAY : time:= 10 ns);
    port( DATABUS : in std_ulogic_vector(3 downto 0):= (others=>'0');
    ACBUS : in std_ulogic_vector(3 downto 0):= (others=>'0');
    OPCODE : in OPTYPE;
    ALUOUT : out std_ulogic_vector(3 downto 0):= (others=>'0'));
    end ALU_ENT;

    architecture ALU_ARCH of ALU_ENT is
    begin
    ALU_PROCESSrocess(DATABUS,ACBUS,OPCODE)

    variable ZWERG : std_logic_vector(3 downto 0):= (others=>'0');
    begin

    ZWERG := (others =>'0');

    case OPCODE is

    when LDAUNM => ZWERG := to_stdlogicvector(DATABUS);
    when ADD => ZWERG := to_stdlogicvector(DATABUS) + to_stdlogicvector(ACBUS);
    when others => null;

    end case;
    ALUOUT <= to_stdulogicvector(ZWERG);

    end process ALU_PROCESS;

    end ALU_ARCH;

    Accumaltor

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;



    entity AKKU_ENT is

    generic(DELAY : time := 10 ns);

    port( CLK : in bit;
    RESET : in bit:='0';
    ALUOUT : in std_ulogic_vector(3 downto 0):="0000";
    DATABUS : out std_logic_vector(3 downto 0):="0000";
    ACBUS : out std_ulogic_vector(3 downto 0):="0000";
    LOADDABUS : in bit:='0';
    LOADACBUS : in bit:='0'
    );

    end AKKU_ENT;

    architecture Behavioral of AKKU_ENT is

    signal ACCU_INTERN : std_ulogic_vector(3 downto 0):="0000";

    begin

    DATABUS_LOADrocess(LOADDABUS,ACCU_INTERN)

    begin

    if LOADDABUS = '1' then

    DATABUS <= to_stdlogicvector(ACCU_INTERN) ;

    else

    DATABUS <= (others=>'Z') ;

    end if;

    end process DATABUS_LOAD;


    AKKU_LOAD: process(CLK,RESET) is

    begin

    if RESET = '1' then

    ACCU_INTERN <= (others=>'0') ;

    elsif CLK'event and CLK = '1' then

    if LOADACBUS = '1' then

    ACCU_INTERN <= ALUOUT ;

    end if;
    end if;

    end process AKKU_LOAD;

    ACBUS <= ACCU_INTERN ;

    end Behavioral;

    Test bench

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;
    use WORK.MP_PACK.ALL;

    ENTITY testbench IS
    END testbench;

    ARCHITECTURE behavior OF testbench IS

    -- Component Declaration
    COMPONENT ALU_AKKU
    port(CLK,RESET : in bit;
    DATABUS : inout std_logic_vector(3 downto 0);
    OPCODE : in OPTYPE;
    LOADDABUS : in bit;
    LOADACBUS : in bit
    );
    END COMPONENT;

    SIGNAL OPCODE : OPTYPE;
    SIGNAL DATABUS : std_logic_vector(3 downto 0) := (others=>'0');
    signal CLK : bit;
    signal RESET : bit;
    signal LOADDABUS : bit;
    signal LOADACBUS : bit;


    BEGIN

    -- Component Instantiation
    uut: ALU_AKKU PORT MAP(
    CLK => CLK,
    RESET => RESET,
    DATABUS => DATABUS,
    OPCODE => OPCODE,
    LOADDABUS=>LOADDABUS,
    LOADACBUS=> LOADACBUS

    );
    -- Test Bench Statements
    ALU_AKKU_CLK: PROCESS
    BEGIN
    wait for 100 ns;
    CLK <= not CLK;

    END PROCESS ALU_AKKU_CLK;

    ALU_AKKU_PROCESSrocess
    begin



    DATABUS <= b"0001" ;
    OPCODE <= LDAUNM;

    for I in 1 to 1 loop
    wait until CLK'event and CLk='1';
    end loop;

    LOADACBUS <= '1';


    for I in 1 to 2 loop
    wait until CLK'event and CLk='1';
    end loop;

    LOADACBUS <= '0';
    DATABUS <= b"0010";
    OPCODE <= ADD ;

    for I in 1 to 1 loop
    wait until CLK'event and CLk='1';

    end loop;

    LOADACBUS <= '1';
    OPCODE <= NOP;

    for I in 1 to 2 loop
    wait until CLK'event and CLk='0';
    end loop;

    LOADACBUS <= '0';
    LOADDABUS <= '1';

    for I in 1 to 1 loop
    wait until CLK'event and CLk='1';
    end loop;

    LOADDABUS <= '0';
    wait;


    end process ALU_AKKU_PROCESS;
    -- End Test Bench
    END;
     
    umerarain, May 18, 2006
    #1
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  2. umerarain

    umerarain

    Joined:
    May 16, 2006
    Messages:
    5
    bidirectional bus problem need help

    hi i posted one query about dat abus conflict,but i didnt got any reply may be i put whole code in this one.any way i just want to know if one can tell me how to reolve data bus conflict.i mean iam taking data from data bus and accumlator to alu and performing opeartion and putting back the data to data bus,and here is the problem when i put data back to data bus,although iam also using output enable signal for this.
    so any one have some idea
    iam attaching two files,one is whole project made in xilinx and other one is arcitecture(problem is line number 4)
    please have a look onto it.
    umer
     
    umerarain, May 23, 2006
    #2
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  3. umerarain

    umerarain

    Joined:
    May 16, 2006
    Messages:
    5
    i forgot to attach the file.
    in zip folder u can see word file and whole software.
    umer
     

    Attached Files:

    umerarain, May 23, 2006
    #3
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