Bidirectional bus in Spartan-3

Discussion in 'VHDL' started by rybol, Sep 9, 2005.

  1. rybol

    rybol Guest

    Hi,

    I am using Spartan-3 XC3S200 and trying to build a bidirectional bus
    ('port_1'). Through this bus I put some data (data_ram_out) from internal
    BRAM to the output of the chip (generator mode) in one situation (signal
    'generator' =1) and sample data from input to BRAM (analyzer mode) in the
    second situation (generator = 0). To make this possible, I used the template
    from ISE Webpack:

    buf_loop: for i in 0 to 7 generate
    begin

    IOBUF_inst : IOBUF
    generic map (
    DRIVE => 12,
    IOSTANDARD => "DEFAULT",
    SLEW => "SLOW")

    port map (
    O => data_0_7(i), -- Buffer output
    IO => port_1(i), -- Buffer inout port (connect directly to
    top-level port)
    I => data_ram_out(i), -- Buffer input
    T => not generator -- 3-state enable input
    );

    end generate buf_loop;

    (My port and signals:

    port_1 : inout std_logic_vector(7 downto 0);

    signal data_0_7 : std_logic_vector(7 donwto 0);
    signal data_ram_out : std_logic_vector(7 downto 0);
    signal generator : std_logic;
    )

    But it seems like only analyzer mode is working ok. (when I make a little
    change: ' T => generator' , only the generator mode works).
    What could I do wrong? Did you ever use the IOBUF with success? Or tried any
    other way of creating a bidirectional bus?

    Regards,
    Tomek
    rybol, Sep 9, 2005
    #1
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  2. rybol

    Andrew FPGA Guest

    Another way is:

    --inside the architecture body
    data_in <= data_bus;
    data_bus <= data_out when drive_bus = '1' else (others => 'Z');

    or

    TristateDriver: process(data_out, drive_bus)
    begin
    if(drive_bus = '1') then
    data_bus <= data_out;
    else
    data_bus <= (others => 'Z');
    end if;
    end process TristateDriver;

    You can also use the .ucf file to assign slew rate, drive strength etc
    properties to IO.

    Regards
    Andrew

    rybol wrote:
    > Hi,
    >
    > I am using Spartan-3 XC3S200 and trying to build a bidirectional bus
    > ('port_1'). Through this bus I put some data (data_ram_out) from internal
    > BRAM to the output of the chip (generator mode) in one situation (signal
    > 'generator' =1) and sample data from input to BRAM (analyzer mode) in the
    > second situation (generator = 0). To make this possible, I used the template
    > from ISE Webpack:
    >
    > buf_loop: for i in 0 to 7 generate
    > begin
    >
    > IOBUF_inst : IOBUF
    > generic map (
    > DRIVE => 12,
    > IOSTANDARD => "DEFAULT",
    > SLEW => "SLOW")
    >
    > port map (
    > O => data_0_7(i), -- Buffer output
    > IO => port_1(i), -- Buffer inout port (connect directly to
    > top-level port)
    > I => data_ram_out(i), -- Buffer input
    > T => not generator -- 3-state enable input
    > );
    >
    > end generate buf_loop;
    >
    > (My port and signals:
    >
    > port_1 : inout std_logic_vector(7 downto 0);
    >
    > signal data_0_7 : std_logic_vector(7 donwto 0);
    > signal data_ram_out : std_logic_vector(7 downto 0);
    > signal generator : std_logic;
    > )
    >
    > But it seems like only analyzer mode is working ok. (when I make a little
    > change: ' T => generator' , only the generator mode works).
    > What could I do wrong? Did you ever use the IOBUF with success? Or tried any
    > other way of creating a bidirectional bus?
    >
    > Regards,
    > Tomek
    Andrew FPGA, Sep 9, 2005
    #2
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  3. rybol

    ajahn Guest

    Hi Tomek,
    you say, both modes work correct when you change the t => (not)
    generator assignment?
    Without taking a closer look, that sounds like your io-buffers work
    okay, but you should check on what the generator signal does: Does it
    switch the correct way?
    Cheers,
    Andreas.
    ajahn, Sep 9, 2005
    #3
  4. rybol

    rybol Guest

    > Hi Tomek,
    > you say, both modes work correct when you change the t => (not)
    > generator assignment?
    > Without taking a closer look, that sounds like your io-buffers work
    > okay, but you should check on what the generator signal does: Does it
    > switch the correct way?
    >


    Of course, the generator signal 'didn't switch the correct way', but now
    everything works fine.
    Thanky you very much! :)

    Tomek
    rybol, Sep 9, 2005
    #4
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