big decoder

Discussion in 'VHDL' started by bxbxb3, Jan 11, 2005.

  1. bxbxb3

    bxbxb3 Guest

    hi,
    I have a total of 13 lines and it must be decoded into 2^13=8192 unique
    lines. Is there any way to reduce the burden of having to type the entire
    number?
     
    bxbxb3, Jan 11, 2005
    #1
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  2. bxbxb3 wrote:

    > hi,
    > I have a total of 13 lines and it must be decoded into 2^13=8192 unique
    > lines. Is there any way to reduce the burden of having to type the entire
    > number?


    How meaningful is it, to have 8192 lines, are you creating a memory?

    Bye Tom
     
    Thomas Reinemann, Jan 11, 2005
    #2
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  3. bxbxb3 a écrit :
    > hi,
    > I have a total of 13 lines and it must be decoded into 2^13=8192 unique
    > lines. Is there any way to reduce the burden of having to type the entire
    > number?


    Quite easy:

    library ieee.
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    ....
    constant n : natural := 13;
    signal addr : std_logic_vector(n-1 downto 0);
    signal lines : std_logic_vector(2**n-1 downto 0);
    ....
    process (addr)
    begin
    lines <= (others => '0');
    lines(to_integer(unsigned(addr))) <= '1';
    end process;
    ....

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Jan 11, 2005
    #3
  4. bxbxb3

    bxbxb3 Guest

    Yes, I am creating a DDR-SDRAM memory module of 8192*256*32 size. Even
    though I prefered complete RTL code, I think will have to code this one in
    behavioral style, thanks to Nicholas Matringe for giving the much needed
    idea.
     
    bxbxb3, Jan 11, 2005
    #4
  5. bxbxb3 wrote:
    > hi,
    > I have a total of 13 lines and it must be decoded into 2^13=8192 unique
    > lines. Is there any way to reduce the burden of having to type the entire
    > number?


    Something along this way (not tested):

    SIGNAL input: std_logic_vector(12 DOWNTO 0);
    SIGNAL output: std_logic_vector(2**13-1 DOWNTO 0);

    VARIABLE out_var: std_logic_vector(2**13-1 DOWNTO 0);
    BEGIN
    out_var := (OTHERS => '0');
    out_var(to_integer(unsigned(input))) := '1';
    ouput <= out_var;
    END
     
    Paul Uiterlinden, Jan 11, 2005
    #5
  6. Paul Uiterlinden a écrit :

    > Something along this way (not tested):
    >
    > SIGNAL input: std_logic_vector(12 DOWNTO 0);
    > SIGNAL output: std_logic_vector(2**13-1 DOWNTO 0);
    >
    > VARIABLE out_var: std_logic_vector(2**13-1 DOWNTO 0);
    > BEGIN
    > out_var := (OTHERS => '0');
    > out_var(to_integer(unsigned(input))) := '1';
    > ouput <= out_var;
    > END


    Why do you use a variable? (just curious)

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Jan 11, 2005
    #6
  7. Nicolas Matringe wrote:
    > Paul Uiterlinden a écrit :
    >
    >> Something along this way (not tested):
    >>
    >> SIGNAL input: std_logic_vector(12 DOWNTO 0);
    >> SIGNAL output: std_logic_vector(2**13-1 DOWNTO 0);
    >>
    >> VARIABLE out_var: std_logic_vector(2**13-1 DOWNTO 0);
    >> BEGIN
    >> out_var := (OTHERS => '0');
    >> out_var(to_integer(unsigned(input))) := '1';
    >> ouput <= out_var;
    >> END

    >
    >
    > Why do you use a variable? (just curious)


    I guess it is not necessary. It was done in a paranoid mood, being
    affraid that "output(some_variable) <= '1'" would create a driver for
    all bits, resulting in all X-s. But that's not the case here (sequential
    signal assignments).

    Paul.
     
    Paul Uiterlinden, Jan 11, 2005
    #7
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