Binding SVA to VHDL std_ulogic_vector

[guarana5]

hi!

i'm trying to bind sva-properties to an existing vhdl project with questasim. most of the ports are of type std_ulogic_vector - and that doesn't work for system verilog. std_ulogic is okay, std_logic_vector as well, but not std_ulogic_vector.

any ideas to work around this issue? i don't want to touch the vhdl design.

sample code:

module sva_wrapper;
bind alu
alu_props alu_sva_bind
   (.c_i(carry_i), .result(result_o), .zero_o(zero_o), .c_o(carry_o));
endmodule

where alu out-port result is of type std_ulogic vector

questasim output:

# ** Error: G:\...\sv\sva_wrapper.sv(12): (vopt-1142) Illegal actual designator type in Verilog port "result" connection.

thank you for your help!
guarana