Bit Error Rate...Implementation..

Discussion in 'VHDL' started by Debashish, Sep 28, 2003.

  1. Debashish

    Debashish Guest

    Hi Guys...

    Can anyone help giving me a good algorithm to implement , BERR in a
    FPGA and that to how many gates it will take consume. I am intend to
    fuse the algo in a Xilinx Virtex Pro. FPGA. Problem is my FPGA is
    already 80% full.

    I heard its pretty difficult to implement a BERR in a FPGA since the
    no. of gates required is too large. So please give me a rough account
    also of the gate level implementation.


    Regards ..
    Debashish Hota
    Debashish, Sep 28, 2003
    #1
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