D
Debashish
Hi Guys...
Can anyone help giving me a good algorithm to implement , BERR in a
FPGA and that to how many gates it will take consume. I am intend to
fuse the algo in a Xilinx Virtex Pro. FPGA. Problem is my FPGA is
already 80% full.
I heard its pretty difficult to implement a BERR in a FPGA since the
no. of gates required is too large. So please give me a rough account
also of the gate level implementation.
Regards ..
Debashish Hota
Can anyone help giving me a good algorithm to implement , BERR in a
FPGA and that to how many gates it will take consume. I am intend to
fuse the algo in a Xilinx Virtex Pro. FPGA. Problem is my FPGA is
already 80% full.
I heard its pretty difficult to implement a BERR in a FPGA since the
no. of gates required is too large. So please give me a rough account
also of the gate level implementation.
Regards ..
Debashish Hota