Bit Reset

[Hans]

Hi

This problem is a bit hard to explain, but I'll try anyway.

I have a register in my system, which contains a bit. When the user writes
a 1 to this bit, it signals to the system that it should perform a task.
Once the task is complete I would like to clear the bit. If the bit isn't
cleared the system will get stuck in an endless loop.

Does anyone know any good techniques for clearing a bit, which is settable
by the user? Or in other words, how can I set the bit in one process and
then clear it in another?

Surely this is a common problem.

Thanks for any help.

 

[rickman]

Hi

This problem is a bit hard to explain, but I'll try anyway.

I have a register in my system, which contains a bit. When the user writes
a 1 to this bit, it signals to the system that it should perform a task.
Once the task is complete I would like to clear the bit. If the bit isn't
cleared the system will get stuck in an endless loop.

Does anyone know any good techniques for clearing a bit, which is settable
by the user? Or in other words, how can I set the bit in one process and
then clear it in another?

You want a finite state machine (FSM). You need at least three states
and possibly four. I'll draw a diagram. Use a non-proportional font to
view.

~TRIGGER ~DONE TRIGGER
--- ----- ------
| | | | | |
V | TRIGGER V | DONE V | ~TRIGGER
+--> IDLE -------> START -------> FINISHED -------+
| |
+------------------------------------------------------+

If your trigger is short enough that it is guaranteed to be gone by the
time the task is done, then you can eliminate the FINISHED state.
Otherwise you will need more than one bit.

--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[rickman]

You want a finite state machine (FSM). You need at least three states
and possibly four. I'll draw a diagram. Use a non-proportional font to
view.

~TRIGGER ~DONE TRIGGER
--- ----- ------
| | | | | |
V | TRIGGER V | DONE V | ~TRIGGER
+--> IDLE -------> START -------> FINISHED -------+
| |
+------------------------------------------------------+

If your trigger is short enough that it is guaranteed to be gone by the
time the task is done, then you can eliminate the FINISHED state.
Otherwise you will need more than one bit.

I sort of goofed up. Just like you need to make sure your TRIGGER
signal is gone before you return to the IDLE state, you need to make
sure your DONE signal is gone before you reach the START state. I guess
you could combine these conditions and still only have a single bit
FSM. But this will depend on the timing of the TRIGGER and DONE signals
and the particulars of your design. For the most general case where you
know nothing about the TRIGGER and DONE signals, you need a four state
machine which will require 2 bits minimum.

--

Rick "rickman" Collins

(e-mail address removed)
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Tom Verbeure]

How about something like this:
- Trigger is a signal from the user
- TaskDone is a signal from the task


process(Clk)
begin
if rising_edge(Clk)
if Trigger = '1' then
ActiveBit <= '1';
end if;

if TaskDone = '1' then
ActiveBit <= '0';
end if;
end process;
This seems to be too straightforward.
Did I miss something?


Tom