bit slice in vectors

Discussion in 'VHDL' started by alb, Sep 12, 2013.

  1. alb

    alb Guest

    Hi everyone,

    I have declared a set of constants in the following way:

    <code>
    constant AB : unsigned(data_t'range) := x"01";
    constant CD : unsigned(data_t'range) := x"02";
    constant EF : unsigned(data_t'range) := x"04";
    constant GH : unsigned(data_t'range) := x"08";
    constant IJ : unsigned(data_t'range) := x"10";
    constant KL : unsigned(data_t'range) := x"20";
    constant MN : unsigned(data_t'range) := x"40";
    constant OP : unsigned(data_t'range) := x"80";
    </code>

    where data_t is a constrained std_logic_vector(7 downto 0) type.
    If we declare a signal/variable foo of data_t type and we want to test
    if bit 'IJ' is set or not, what I'm currently doing is the following:

    <code>
    if foo(to_integer(IJ) - 1) then
    -- do stuff
    end if;
    </code>

    which I find rather ugly... And if the constant is an slv than I would
    need to do something like

    <code>
    if foo(to_integer(unsigned(IJ) - 1)) then
    -- do stuff
    end if;
    </code>

    which is even uglier!

    Is there a more readable way to do that?
    True I can write my function to handle the conversions and return a
    natural, but I didn't want to reinvent the wheel :)

    On top of this, the limitation of this approach is that if data_t change
    bus width the constants definitions will not work anymore. Any idea?

    Thanks a lot,

    Al

    --
    A: Because it fouls the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
    alb, Sep 12, 2013
    #1
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  2. alb

    KJ Guest

    On Thursday, September 12, 2013 8:53:27 AM UTC-4, alb wrote:

    It's not clear to me why 'IJ' is anything other than an integer in your example. That would clean up most of what you seem to not like.

    As for a cleaner overall approach, presumably the reason that you're defining all of those constants is because the data should really be defined as arecord and there is a need to convert between the record type and std_logic_vectors. There probably isn't much value in your current definition of 'data_t' type as being just another vector. Take a look at this post...

    https://groups.google.com/forum/?hl=en#!searchin/comp.lang.vhdl/to_std_ulogic_vector$20jennings/comp.lang.vhdl/9s7wXZUWqrQ/-K2fqq-YfGkJ

    Kevin Jennings
    KJ, Sep 12, 2013
    #2
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  3. alb

    Andy Guest

    Al,

    I would encourage to you to use integers (or subtypes thereof) wherever possible, particularly in places where unknown or tri-state representation is not needed, and the representation size is <= 31 bits unsigned or 32 bits signed.

    And as Kevin said, especialy for your constants.

    If the constants are also needed in unsigned/slv form, consider which is easier or less common in your application: converting slv/unsigned to integer, or integer to slv/unsigned?

    Andy
    Andy, Sep 12, 2013
    #3
  4. alb

    alb Guest

    Hi KJ,

    On 12/09/2013 17:56, KJ wrote:
    > It's not clear to me why 'IJ' is anything other than an integer in
    > your example. That would clean up most of what you seem to not
    > like.


    because sometimes your 'emergency exit might be located just behind you'!

    > As for a cleaner overall approach, presumably the reason that you're
    > defining all of those constants is because the data should really be
    > defined as a record and there is a need to convert between the record
    > type and std_logic_vectors. There probably isn't much value in your
    > current definition of 'data_t' type as being just another vector.


    Constants definition is used, for example, in an interrupt enable
    register assignment which can be easily performed this way:

    <code>
    interrupt_reg := PD or PDE or TBE;
    </code>

    or equivalently in the case of integer defined constants:

    <code>
    interrupt_reg(PD) := '1';
    interrupt_reg(PDE) := '1';
    interrupt_reg(TBE) := '1';
    </code>

    And by the way I just found that in the OP there's a mistake in the
    conversion, since it will only work for bit 1 and 2...!!!

    > Take a look at this post...
    >
    > https://groups.google.com/forum/?hl=en#!searchin/comp.lang.vhdl/to_std_ulogic_vector$20jennings/comp.lang.vhdl/9s7wXZUWqrQ/-K2fqq-YfGkJ


    That post inspired me a great deal and now I do have conversion
    functions from/to my record types.
    alb, Sep 13, 2013
    #4
  5. alb

    Andy Guest

    Al,

    Assuming the integer constants are locally static:

    interrupt_reg := (PD | PDE | TBE => '1', others => '0');

    would also work.

    Where there is a will, there is a way.
    Circumstances dictate whether the will is worth the way.

    Andy
    Andy, Sep 16, 2013
    #5
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