bit vs std_logic ?

Discussion in 'VHDL' started by Squidge, May 28, 2005.

  1. Squidge

    Squidge Guest

    Can anyone tell me any disadvantages of using 'std_logic' over the builtin
    type 'bit'? I'm still learning VHDL, and the books and tutorials I've read
    all use 'bit' and 'bit_vector', but I find 'std_logic' and
    'std_logic_vector' much more flexible. For example, when creating a
    prescaler for an input clock, I normally like to use a simple counter and
    assign the clock pin to one of the bits of the counter. I can't work out
    how to use a bit_vector as a counter without errors stating that
    bit_vector's don't support the '+' operator.

    So, can std_logic suitably replace the 'bit' operator, or are there places
    where 'bit' would be more suitable ? (flexibility, speed reasons, etc)
     
    Squidge, May 28, 2005
    #1
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  2. Squidge

    Neo Guest

    std_logic models all four states '1', '0', 'X', 'Z' while bit takes
    only '0'and '1'.
     
    Neo, May 30, 2005
    #2
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  3. Squidge

    jandc Guest

    > std_logic models all four states '1', '0', 'X', 'Z' while bit takes
    > only '0'and '1'.
    >

    to be more exact: std_logic models all 9 states: '1', '0', 'X', 'Z',
    'U', '-', 'L', 'H', 'W'
     
    jandc, May 30, 2005
    #3
  4. Mike Treseler, May 31, 2005
    #4
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