black box module integration

Discussion in 'VHDL' started by Serkan, Jan 13, 2010.

  1. Serkan

    Serkan Guest

    Dear Veterans,

    I have a design for FPGA whose top module includes 15 vhdl modules
    a flexible user/client block that interacts with these blocks . I do
    not have the source code for the user block. I just have the inputs
    and outputs of this block. I instantiated user block as a black box in
    my design. We want to integrate user block into my design without
    interchanging the source code from both sides. However, the issue is
    that "the synthesis should be done in client's side" and I have the
    top module. It should be in a way that once I send the files I am
    done. To the client, I want to supply the synthesized version of the
    code which client will work for 6 months or so on their user block.
    During this time, I will not bother generation of a programming file
    for them. I want to make sure they have all the necessary files in
    this period.

    questions
    1- Is there a way other than sending my top module and other 15 edifs
    to the client.
    2- Is it possible for me to insert client's block as a black box, make
    a synthesis and send this file with the ucf file to the client and
    make sure that client can integrate his user block and can work
    further and generate a programming file.
    3- Do I have to make a new top module that has two blocks. One of
    this block is my previous top module the other is the user block? I
    will put all inputs and outputs of user block to my previous top
    module's inputs and outputs in a way that that user block
    functionality stays the same.

    I prefer 2,3,1. I hope option 2 is aplicable.

    I am using Xilinx 9.1.03i, XST,VHDL
    Serkan, Jan 13, 2010
    #1
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  2. Serkan

    Serkan Guest

    It seems our veterans are not familiar with the subject.
    any comments anyone?

    Serkan
    Serkan, Jan 14, 2010
    #2
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  3. On Thu, 14 Jan 2010 00:18:01 -0800 (PST), Serkan wrote:

    >It seems our veterans are not familiar with the subject.


    Wrong veterans, wrong subject.

    Your problem is not really anything to do with VHDL; it's
    a tool issue. comp.arch.fpga would serve you better.
    Mention which specific synthesis and mapping tools
    you are using; it matters.

    Personally I have almost no idea; it's the sort of thing
    I know is probably do-able, and I'll have to look it up
    in the docs (or find an example) if I need to do it.
    --
    Jonathan Bromley
    Jonathan Bromley, Jan 14, 2010
    #3
  4. On Thu, 14 Jan 2010 09:41:51 +0100, Jonathan Bromley wrote:

    >Wrong veterans, wrong subject.


    oh, OK, you posted to comp.arch.fpga too.

    I'm slightly surprised you didn't get a response
    there. Not everyone follows these groups daily,
    though; it's worth waiting a while.
    --
    Jonathan Bromley
    Jonathan Bromley, Jan 14, 2010
    #4
  5. Serkan

    Serkan Guest

    On Jan 14, 10:43 am, Jonathan Bromley <>
    wrote:
    > On Thu, 14 Jan 2010 09:41:51 +0100, Jonathan Bromley wrote:
    > >Wrong veterans, wrong subject.

    >
    > oh, OK, you posted to comp.arch.fpga too.
    >
    > I'm slightly surprised you didn't get a response
    > there.  Not everyone follows these groups daily,
    > though; it's worth waiting a while.
    > --
    > Jonathan Bromley



    Currently, I am doing the 3rd option.
    If I got response from other forums, It will be a good know-how for
    me.
    I'm also surprised to find a case that you do not know of :)
    But, thank you very much Mr Bromley.

    serkan
    Serkan, Jan 14, 2010
    #5
  6. On Thu, 14 Jan 2010 06:50:06 -0800 (PST), Serkan wrote:

    >I'm also surprised to find a case that you do not know of :)


    Flattery will get you everywhere :)

    I'm a language/RTL/verification guy. Tools, and
    especially integrated FPGA tools, are a necessary evil.
    Often when reading comp.arch.fpga, and when watching
    experienced FPGA users at work, I'm astonished by
    the cunning and time-saving things folk can do with
    their development tools.

    Luckily for us all, there's a market for many different
    skill sets in this industry!
    --
    Jonathan Bromley
    Jonathan Bromley, Jan 14, 2010
    #6
  7. Serkan wrote:

    > I have a design for FPGA whose top module includes 15 vhdl modules
    > a flexible user/client block that interacts with these blocks . I do
    > not have the source code for the user block.


    It's much simpler using source code.
    Without source code, this is not a vhdl question.

    -- Mike Treseler
    Mike Treseler, Jan 14, 2010
    #7
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