X
Xin Xiao
I have a 65,535 x 16 bit RAM and my synthesis tool is using Distributed RAM
instead of Block RAM. I am told this is not efficient. I have a smaller RAM
and it is actually synthesized using Block RAM. How can I design in VHDL a
65,535 x 16-bit RAM using Block RAM? Or this is not possible?
Thanks,
instead of Block RAM. I am told this is not efficient. I have a smaller RAM
and it is actually synthesized using Block RAM. How can I design in VHDL a
65,535 x 16-bit RAM using Block RAM? Or this is not possible?
Thanks,